February 2005
Copyright © Alliance Semiconductor. All rights reserved.
®
AS7C331MPFD32A
AS7C331MPFD36A
2/10/05, v.1.1 Alliance Semiconductor 1 of 19
3.3V 1M × 32/36 pipelined burst synchronous SRAM
Features
• Organization: 1,048,576 words × 32 or 36 bits
• Fast clock speeds to 200 MHz
• Fast clock to data access: 3.1/3.5/3.8 ns
•Fast OE access time: 3.1/3.5/3.8 ns
• Fully synchronous register-to-register operation
• Double-cycle deselect
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and global write
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V
DDQ
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
Logic block diagram
Selection guide
-200 -166 -133 Units
Minimum cycle time 5 6 7.5 ns
Maximum clock frequency 200 166 133 MHz
Maximum clock access time 3.1 3.5 3.8 ns
Maximum operating current 450 400 350 mA
Maximum standby current 170 150 140 mA
Maximum CMOS standby current (DC) 90 90 90 mA
A[19:0]
20 18 2020
Q0
Q1
1M × 32/36
Memory
array
Burst logic
CLK
CLR
CE
Address
DQ
CE
CLK
DQ
d
CLK
DQ
Byte write
registers
register
DQ
c
CLK
DQ
Byte write
registers
DQ
b
CLK
DQ
Byte write
registers
DQ
a
CLK
DQ
Byte write
registers
Enable
CLK
DQ
register
Enable
CLK
DQ
delay
register
CE
Output
registers
Input
registers
Power
down
DQ[a:d]
4
32/36
GWE
BWE
BW
d
ADV
ADSC
ADSP
CLK
CE0
CE1
CE2
BW
c
BW
b
BW
a
OE
ZZ
LBO
OE
CLK CLK
32/36
32/36
22