December 2004
Copyright © Alliance Semiconductor. All rights reserved.
®
AS7C331MNTF18A
12/23/04, v 1.2 Alliance Semiconductor P. 1 of 18
3.3V 1M x 18 Flowthrough Synchronous SRAM with NTD
TM
Features
• Organization: 1,048,576 words × 18 bits
•NTD
™
architecture for efficient bus operation
• Fast clock to data access: 7.5/8.5/10 ns
•Fast OE access time: 3.5/4.0 ns
• Fully synchronous operation
• Flow-through mode
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and global write
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V
DDQ
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
Logic block diagram
Selection guide
-75 -85 -10 Units
Minimum cycle time 8.5 10 12 ns
Maximum clock access time 7.5 8.5 10 ns
Maximum operating current 275 250 230 mA
Maximum standby current 90 80 80 mA
Maximum CMOS standby current (DC) 60 60 60 mA
W
r
it
e Buf
f
er
Address
D Q
CLK
register
Output
buffer
DQ [a,b]
20
20
CLK
CE0
CE1
CE2
A[19:0]
OE
CEN
Control
CLK
logic
Data
D
Q
CLK
input
register
18 18
OE
1M x 18
SRAM
array
R/W
DQ [a,b]
BWa
BWb
CLK
QD
ADV / LD
LBO
burst logic
addr. registers
Write delay
20
ZZ
CLK
18 18
18
18