December 2004
Copyright © Alliance Semiconductor. All rights reserved.
®
AS7C33128PFS32B
AS7C33128PFS36B
3.3V 128K X 32/36 pipeline burst synchronous SRAM
12/10/04; v.1.7 Alliance Semiconductor P. 1 of 19
Features
• Organization: 131,072 words × 32 or 36 bits
• Fast clock speeds to 200 MHz
• Fast clock to data access: 3.0/3.5/4.0 ns
•Fast OE access time: 3.0/3.5/4.0 ns
• Fully synchronous register-to-register operation
• Single-cycle deselect
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and global write
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V
DDQ
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
Logic block diagram
Q0
Q1
128K × 32/36
Memory
array
Burst logic
CLK
CLR
CE
Address
DQ
CE
CLK
DQ
d
CLK
DQ
Byte write
registers
register
DQ
c
CLK
DQ
Byte write
registers
DQ
b
CLK
DQ
Byte write
registers
DQ
a
CLK
DQ
Byte write
registers
Enable
CLK
DQ
register
Enable
CLK
DQ
delay
register
CE
Output
registers
Input
registers
Power
down
4
36/32
171517
17
GWE
BWE
BW
d
ADV
ADSC
ADSP
CLK
CE0
CE1
CE2
BW
c
BW
b
BW
a
OE
A[16:0]
ZZ
LBO
OE
CLK CLK
36/32
36/32
DQ [a:d]
Selection guide
–200 –166 –133 Units
Minimum cycle time 5 6 7.5 ns
Maximum clock frequency 200 166 133 MHz
Maximum clock access time 3.0 3.5 4 ns
Maximum operating current 375 350 325 mA
Maximum standby current 130 100 90 mA
Maximum CMOS standby current (DC) 30 30 30 mA