April 2005
Copyright © Alliance Semiconductor. All rights reserved.
®
AS7C33128NTD18B
4/28/05; v.1.3 Alliance Semiconductor P. 1 of 19
3.3V 128K×18 Pipelined SRAM with NTD
TM
Features
• Organization: 131,072 words × 18 bits
•NTD
™
architecture for efficient bus operation
• Fast clock speeds to 200 MHz
• Fast clock to data access: 3.0/3.5/4.0 ns
•Fast OE access time: 3.0/3.5/4.0 ns
• Fully synchronous operation
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V
DDQ
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
Logic block diagram
W
r
ite B
u
f
f
er
Address
D Q
CLK
register
Output
Register
DQ [a:b]
18
18
17
17
CLK
CE0
CE1
CE2
A[16:0]
OE
CLK
CEN
Control
CLK
logic
DataD
Q
CLK
Input
Register
18 18
18
OE
128K x 18
SRAM
Array
R/W
DQ [a:b]
BWa
BWb
CLK
QD
ADV / LD
LBO
Burst logic
addr. registers
Write delay
18
17
ZZ
CLK
17
Selection Guide
-200 -166 -133 Units
Minimum cycle time 5 67.5ns
Maximum clock frequency 200 166 133 MHz
Maximum clock access time 3.0 3.5 4 ns
Maximum operating current 375 350 325 mA
Maximum standby current 135 120 110 mA
Maximum CMOS standby current (DC) 30 30 30 mA