March 2005
Preliminary Information
Copyright © Alliance Semiconductor. All rights reserved.
AS7C3256A-8
3/22/05; v.1.0 Alliance Semiconductor P. 1 of 9
3.3V 32K X 8 CMOS SRAM (Common I/O)
®
Features
• Organization: 32,768 words × 8 bits
• High speed
- 8 ns address access time
- 5 ns output enable access time
• Very low power consumption: ACTIVE
- 216mW max @ 8 ns
• Very low power consumption: STANDBY
- 7.2 mW max CMOS I/O
• Easy memory expansion with CE and OE inputs
• TTL-compatible, three-state I/O
• 28-pin JEDEC standard packages
- 300 mil SOJ
-8 × 13.4 mm TSOP 1
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
A
9
A
8
256 X 128 X 8
Array
(262,144)
Input buffer
A0
A1
A2
A3
A4
A5
A6
A7
A
10
A
11
A
12
A
13
A
14
I/O0
I/O7
V
CC
GND
OE
CE
WE
Column decoder
Row decode
r
Control
circuit
S
e
ns
e
amp
Pin arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
WE
A13
A8
A9
A11
OE A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
A14
A12
A7
A6
A5
A4
A3 A2
A1
A0
I/O0
I/O1
I/O2
GNDAS7C3256A
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
AS7C
3256A
16
15
28-pin TSOP 1 (8×13.4 mm) 28-pin SOJ (300 mil)
Selection guide
-8 Unit
Maximum address access time 8 ns
Maximum output enable access time 5 ns
Maximum operating current 60 mA
Maximum CMOS standby current 2 mA