February 2005
Preliminary Information
Copyright © Alliance Semiconductor. All rights reserved.
®
AS7C32098A
3.3 V 128K × 16 CMOS SRAM
2/24/05, v. 1.0 Alliance Semiconductor P. 1 of 10
Features
• Industrial and commercial temperature
• Organization: 131,072 words × 16 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 4/5/6/7 ns output enable access time
• Low power consumption: ACTIVE
- 650 mW /max @ 10 ns
• Low power consumption: STANDBY
-28.8 mW /max CMOS
• Individual byte read/write controls
• Easy memory expansion with CE, OE inputs
• TTL- and CMOS-compatible, three-state I/O
• 44-pin JEDEC standard packages
- TSOP 2
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
1024 × 128 × 16
Array
(2,097,152)
OE
CE
WE
Column decoder
Ro
w D
e
c
o
d
e
r
A0
A1
A2
A3
A4
A6
A7
A8
V
CC
GND
A12
A5 A9
A10 A1
1
A14 A15 A16
A13
Control circuit
I/O1–I/O8
I/O9–I/O16
UB
LB
I/O
buffer
Pin arrangement for TSOP 2
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O14
I/O13
GND
V
CC
I/O12
I/O11
I/O10
I/O9
NC
A13
A12
A11
A10
NC
A4
CE
I/O1
I/O2
I/O3
I/O4
V
CC
GND
I/O5
I/O6
I/O7
I/O8
WE
A5
A6
A7
21
22
A8
A9
UB
LB
I/O16
I/O15
2A1
3A2
4A3
1A0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44
A15
A14
OE
A16
Selection guide
–10 –12 –15 –20 Unit
Maximum address access time 10 12 15 20 ns
Maximum output enable access time 4 5 6 7 ns
Maximum operating current
Industrial 180 160 140 110 mA
Commercial 170 150 130 100 mA
Maximum CMOS standby current 8 8 8 8 mA