December 2004
Copyright © Alliance Semiconductor. All rights reserved.
®
AS7C25512NTD32A
AS7C25512NTD36A
12/23/04, v 2.2 Alliance Semiconductor P. 1 of 18
2.5V 512K × 32/36 Pipelined SRAM with NTD
TM
Features
• Organization: 524,288 words × 32 or 36 bits
•NTD
™
architecture for efficient bus operation
• Fast clock speeds to 166 MHz
• Fast clock to data access: 3.5/3.8 ns
•Fast OE access time: 3.5/3.8 ns
• Fully synchronous operation
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and global write
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 2.5V core power supply
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
Logic block diagram
Selection guide
-166 -133 Units
Minimum cycle time 6 7.5 ns
Maximum clock frequency 166 133 MHz
Maximum clock access time 3.5 3.8 ns
Maximum operating current 290 270 mA
Maximum standby current 85 75 mA
Maximum CMOS standby current (DC) 40 40 mA
W
r
i
t
e B
u
f
f
er
Address
D Q
CLK
register
Output
Register
DQ[a,b,c,d]
19
19
CLK
CE0
CE1
CE2
A[18:0]
OE
CLK
CEN
Control
CLK
logic
Data
D
Q
CLK
Input
Register
32/36
32/36
OE
512K x 32/36
SRAM
Array
R/W
DQ[a,b,c,d]
BWb
BWd
CLK
QD
ADV / LD
LBO
Burst logic
addr. registers
Write delay
19
ZZ
CLK
32/36 32/36
32/36
32/36
BWc
BWa