January 2005
Copyright © Alliance Semiconductor. All rights reserved.
®
AS7C252MNTD18A
1/17/05, V 1.2 Alliance Semiconductor P. 1 of 18
2.5V 2M × 18 Pipelined SRAM with NTD
TM

Features
• Organization: 2,097,152 words × 18 bits
•NTD
™
architecture for efficient bus operation
• Fast clock speeds to 200 MHz
• Fast clock to data access: 3.2/3.5/3.8 ns
•Fast OE access time: 3.2/3.5/3.8 ns
• Fully synchronous operation
• Pipelined mode
• Common data inputs and data outputs
• Asynchronous output enable control
• Available in 100-pin TQFP packages
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 2.5V core power supply
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
Logic block diagram
Selection guide
-200 -166 -133 Units
Minimum cycle time 5 6 7.5 ns
Maximum clock frequency 200 166 133 MHz
Maximum clock access time 3.2 3.5 3.8 ns
Maximum operating current 450 400 350 mA
Maximum standby current 170 150 140 mA
Maximum CMOS standby current (DC) 90 90 90 mA
W
r
i
t
e Bu
f
f
er
Address
D Q
CLK
register
Output
Register
DQ[a,b]
21
21
CLK
CE0
CE1
CE2
A[20:0]
OE
CLK
CEN
Control
CLK
logic
Data
D
Q
CLK
Input
Register
18
18
OE
2 M x 18
SRAM
Array
R/W
DQ[a,b]
BWb
CLK
QD
ADV / LD
LBO
Burst logic
addr. registers
Write delay
21
ZZ
CLK
18 18
18
18
BWa