February 2005
Copyright © Alliance Semiconductor. All rights reserved.
®
AS7C251MPFD18A
2/10/05, v. 1.2 Alliance Semiconductor 1 of 19
2.5V 1M x 18 pipelined burst synchronous SRAM
Features
• Organization: 1,048,576 x18 bits
• Fast clock speeds to 166 MHz
• Fast clock to data access: 3.5/3.8 ns
•Fast OE access time: 3.5/3.8 ns
• Fully synchronous register-to-register operation
• Double-cycle deselect
• Asynchronous output enable control
• Available 100-pin TQFP package
• Individual byte write and global write
• Multiple chip enables for easy expansion
• 2.5V core power supply
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
Logic block diagram
Selection guide
-166 -133 Units
Minimum cycle time 6 7.5 ns
Maximum clock frequency 166 133 MHz
Maximum clock access time 3.5 3.8 ns
Maximum operating current 290 270 mA
Maximum standby current 85 75 mA
Maximum CMOS standby current (DC) 40 40 mA
Burst logic
ADV
ADSC
ADSP
CLK
LBO
CLK
CLR
CS
201820
A[19:0]
20
Address
D Q
CS
CLK
register
1M x 18
Memory
array
1818
DQb
CLK
DQ
Byte Write
registers
DQa
CLK
DQ
Byte Write
registers
Enable
CLK
DQ
register
Enable
CLK
DQ
delay
register
CE
Output
registers
Input
registers
Power
down
DQ[a,b]
2
CE0
CE1
CE2
BW
b
BW
a
OE
ZZ
OE
CLK
CLK

BWE
GWE
18