December 2004
Copyright © Alliance Semiconductor. All rights reserved.
®
AS7C251MFT18A
12/24/04, v. 1.2 Alliance Semiconductor 1 of 19
2.5V 1M x 18 flowthrough burst synchronous SRAM
Features
• Organization: 1,048,576 words x18 bits
• Fast clock to data access: 7.5/8.5/10 ns
•Fast OE access time: 3.5/4.0 ns
• Fully synchronous flow-through operation
• Asynchronous output enable control
• Available 100-pin TQFP package
• Individual byte write and global write
• Multiple chip enables for easy expansion
• 2.5V core power supply
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
Logic block diagram
Selection guide
-75 -85 -10 Units
Minimum cycle time 8.5 10 12 ns
Maximum clock access time 7.5 8.5 10 ns
Maximum operating current 275 250 230 mA
Maximum standby current 90 80 80 mA
Maximum CMOS standby current (DC) 60 60 60 mA
Burst logic
ADV
ADSC
ADSP
CLK
LBO
CLK
CLR
CS
201820
A[19:0]
20
Address
D Q
CS
CLK
register
1M x 18
Memory
array
1818
DQb
CLK
DQ
Byte Write
registers
DQa
CLK
DQ
Byte Write
registers
Enable
CLK
DQ
register
Enable
CLK
DQ
delay
register
CE
Output
buffers
Input
registers
Power
down
DQ[a,b]
2
CE0
CE1
CE2
BW
b
BW
a
OE
ZZ
OE
CLK

BWE
GWE
18