March 2004
Copyright © Alliance Semiconductor. All rights reserved.
®
AS7C1026B
5 V 64K X 16 CMOS SRAM
3/26/04, v 1.3 Alliance Semiconductor P. 1 of 10
Features
• Industrial and commercial versions
• Organization: 65,536 words × 16 bits
• Center power and ground pins for low noise
• High speed
- 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
• Low power consumption: ACTIVE
- 605 mW / max @ 10 ns
• Low power consumption: STANDBY
- 55 mW / max CMOS I/O
• 6 T 0.18 u CMOS technology
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• JEDEC standard packaging
- 44-pin 400 mil SOJ
- 44-pin TSOP 2-400
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
64 K × 16
Array
OE
CE
WE
Column decoder
Row d
e
cod
e
r
A0
A1
A2
A3
A4
A5
A7
V
CC
GND
A8 A9
A1
0
A1
1
A1
2
A1
3
A1
4
A1
5
Control circuit
I/O0–I/O7
I/O8–I/O15
UB
LB
I/O
buffer
A6
Pin arrangement
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O13
I/O12
GND
V
CC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
A0
CE
I/O0
I/O1
I/O2
I/O3
V
CC
GND
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
44-Pin SOJ (400 mil), TSOP 2
21
22
A12
NC
UB
LB
I/O15
I/O14
2A3
3A2
4A1
1A4
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44
A6
A7
OE
A5
AS7C10
26B
Selection guide
-10 -12 -15 -20 Unit
Maximum address access time 10 12 15 20 ns
Maximum output enable access time 5678ns
Maximum operating current 110 100 90 80 mA
Maximum CMOS standby current 10 10 10 10 mA