March 2004
Copyright © Alliance Semiconductor. All rights reserved.
®
AS7C1025B
5V 128K X 8 CMOS SRAM (Center power and ground)
3/26/04, v. 1.3 Alliance Semiconductor P. 1 of 9
Features
• Industrial and commercial temperatures
• Organization: 131,072 x 8 bits
• High speed
- 10/12/15/20 ns address access time
- 5/6/7/8 ns output enable access time
• Low power consumption: ACTIVE
- 605mW / max @ 10 ns
• Low power consumption: STANDBY
- 55 mW / max CMOS
• 6 T 0.18 u CMOS technology
• Easy memory expansion with CE, OE inputs
• Center power and ground
• TTL/LVTTL-compatible, three-state I/O
• JEDEC-standard packages
- 32-pin, 300 mil SOJ
- 32-pin, 400 mil SOJ
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
512 x 256 x 8
Array
(1,048,576)
Se
nse a
m
p
Input buffer
A10 A1
1
A12 A13 A14 A15 A16
I/O0
I/O7
OE
CE
WE
Column decoder
Row de
code
r
Control
circuit
A9
A0
A1
A2
A3
A4
A5
A6
A7
V
CC
GND
A8
Pin arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE
I/O7
I/O6
GND
V
CC
I/O5
I/O4
A12
A11
A10
A9
A8
A0
A1
A2
A3
CE
I/O0
I/O1
V
CC
GND
I/O2
I/O3
WE
A4
A5
A6
A7
AS7C10
25B
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
Selection guide
-10 -12 -15 -20 Unit
Maximum address access time 10 12 15 20 ns
Maximum output enable access time 5 6 7 8 ns
Maximum operating current 110 100 90 80 mA
Maximum CMOS standby current 10 10 10 10 mA