November 2000
Copyright ©2000 Alliance Semiconductor. All rights reserved.
®
AS7C1024
AS7C31024
11/29/00 ALLIANCE SEMICONDUCTOR 1
5V/3.3V 128K×8 CMOS SRAM (Evolutionary Pinout)
Features
• AS7C1024 (5V version)
• AS7C31024 (3.3V version)
• Industrial and commercial temperatures
• Organization: 131,072 words × 8 bits
•High speed
- 10/12/15/20 ns address access time
- 5/6/8/10 ns output enable access time
• Low power consumption: ACTIVE
- 825 mW (c) / max @ 12 ns
- 360 mW (AS7C31024) / max @ 12 ns
• Low power consumption: STANDBY
- 55 mW (AS7C1024) / max CMOS
- 36 mW (AS7C31024) / max CMOS
• 2.0V data retention
• Easy memory expansion with CE1, CE2, OE inputs
• TTL/LVTTL-compatible, three-state I/O
• 32-pin JEDEC standard packages
- 300 mil SOJ
- 400 mil SOJ
-8 × 20mm TSOP I
- 8 × 13.4 mm sTSOP I
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
512×256×8
Array
(1,048,576)
S
e
n
se a
m
p
Input buffer
A1
0
A1
1
A1
2
A1
3
A1
4
A1
5
A1
6
I/O0
I/O7
OE
CE1
WE
Column decoder
Ro
w
dec
o
d
e
r
Control
circuit
A9
A0
A1
A2
A3
A4
A5
A6
A7
V
CC
GND
A8
CE2
Pin arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND


32-pin SOJ (300 mil)
V
CC
A15
CE2
WE
A13
A8
A9
A11 OE
A10
CE1
I/O7
I/O6
I/O4
NC
A16
A14
A12
A7
A6
A5
A4 A3
A2
A1
A0
I/O0
I/O1
32-pin TSOP I
I/O2
GND
I/O5
I/O3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
31
30
29
28
27
26
25
24
23
22
21
A
S
7C
1024
A
S
7C
31024
20
19
15
16
18
17
(8 x 20mm)
32-pin SOJ (400 mil)
Selection guide
Shaded areas contain advance information.
AS7C1024-10
AS7C31024-10
AS7C1024-12
AS7C31024-12
AS7C1024-15
AS7C31024-15
AS7C1024-20
AS7C31024-20 Unit
Maximum address access time 10 12 15 20 ns
Maximum output enable access time 56810ns
Maximum operating current
AS7C1024 150 140 125 110 mA
AS7C31024 100 90 80 75 mA
Maximum CMOS standby current
AS7C1024 10 10 10 15 mA
AS7C31024 10 10 10 15 mA