Advance information
Copyright ©2000 Alliance Semiconductor. All rights reserved.
®
AS4LC8M8S0
AS4LC4M16S0
7/5/00 ALLIANCE SEMICONDUCTOR 1
3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM
Features
• PC100/133 compliant
• Organization
- 2,097,152 words × 8 bits × 4 banks (8M×8)
- 1,048,576 words × 16 bits × 4 banks (4M×16)
• Fully synchronous
- All signals referenced to positive edge of clock
• Four internal banks controlled by BA0/BA1 (bank select)
•High speed
- 133/125/100 MHz
- 5.4 ns (133 MHz)/6 ns (125/100 MHz) clock access time
• Low power consumption
- Standby: 7.2 mW max, CMOS I/O
• 4096 refresh cycles, 64 ms refresh interval
• Auto refresh and self refresh
• Automatic and direct precharge
• Burst read, single write operation
• Can assert random column address in every cycle
• LVTTL compatible I/O
• 3.3V power supply
• JEDEC standard package, pinout and function
- 400 mil, 54-pin TSOP II
• Read/write data masking
• Programmable burst length (1/2/4/8/full page)
• Programmable burst sequence (sequential/interleaved)
• Programmable CAS latency (2/3)
Pin arrangement
A3
V
CC
A4
V
SS
V
CC
DQ0
V
CCQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
CCQ
DQ5
DQ6
V
SSQ
DQ7
V
CC
LDQM
V
SS
DQ15
V
SSQ
DQ14
DQ13
V
CCQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
CCQ
DQ8
V
SS
NC
UDQM
CLK
CKE
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
54-
p
i
n T
S
O
P
23
24
25
32
31
30
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
NC
A11
A9
A8
A7
A6
A5
26
27
29
28
NC
DQ1
NC
DQ2
NC
DQ3
NC
NC
DQ7
NC
DQ6
NC
DQ5
NC
DQ4
NC
DQM
4L
C
4
M1
6S
0
A3
V
CC
V
CC
DQ0
V
CCQ
V
SSQ
V
CCQ
V
SSQ
V
CC
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A4
V
SS
V
SS
V
SSQ
V
CCQ
V
SSQ
V
CCQ
V
SS
NC
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
AS4LC4M16S0
AS4LC4M16S0
Pin designation
Pin(s) Description
DQM (8M×8)
UDQM/LDQM (4M×16)
Output disable/write mask
A0 to A11 Address inputs
BA0, BA1 Bank select inputs
DQ0 to DQ7 (8M×8)
DQ0 to DQ15 (4M×16)
Input/output
RAS Row address strobe
CAS Column address strobe
WE Write enable
CS Chip select
V
CC
, V
CCQ
Power (3.3V ± 0.3V)
V
SS
, V
SSQ
Ground
CLK Clock input
CKE Clock enable
Selection guide
Symbol -75 (PC133) -8 -10F (PC100) -10 (PC100) Unit
Bus frequency f
max
133 125 100 100 MHz
Minimum clock access time
CL = 2 t
AC
––6–ns
CL = 3 t
AC
5.4 6 – 6 ns
Minimum setup time t
S
1.5 2 2 2 ns
Minimum hold time t
H
0.81.01.01.0ns
Minimum RAS to CAS delay t
RCD
3323cyle
Minimum RAS precharge time t
RP
s
Remarks: (CL/t
RCD
/t
RP
) 3/3/3 3/3/3 2/2/2 3/3/3