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Copyright ©1998 Alliance Semiconductor. All rights reserved.
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• Organization: 256K×8 or 128K×16
• Sector architecture
- One 16K; two 8K; one 32K; and three 64K byte sectors
- Boot code sector architecture—T (top) or B (bottom)
- Erase any combination of sectors or full chip
• Single 5.0±0.5V power supply for read/write operations
• Sector protection
• High speed 55/70/90/120 ns address access time
• Automated on-chip programming algorithm
- Automatically programs/verifies data at specified ad-
dress
• Automated on-chip erase algorith
- Automatically preprograms/erases chip or specified sec-
tors
• 10,000 write/erase cycle endurance
• Hardware RESET pin
- Resets internal state machine to read mode
• Low power consumption
- 20 mA typical read current
- 30 mA typical program current
- 300 µA typical standby current
- 1 µA typical standby current (RESET = 0)
• JEDEC standard software, packages and pinouts
-48-pin TSOP
-44-pin SO
• Detection of program/erase cycle completion
-DQ7 DATA polling
- DQ6 toggle bit
- RY/BY output
• Erase suspend/resume
- Supports reading data from a sector not being erased
• Low V
CC
write lock-out below 2.8V
/RJLF#EORFN#GLDJUDP
X decoder
V
CC
V
SS
Cell matrix
Y decoder Y gating
Data latchChip enable
A
d
dr
es
s
la
t
c
h
Input/output
buffers
Sector protect
Command
register
Program/erase
control
V
CC
detector
Erase voltage
generator
Program voltage
generator
Timer
A0–A16
CE
OE
STB
STB
Output enable
Logic
RY/BY
WE
BYTE
RESET
DQ0–DQ15
switches
A-1
3LQ#DUUDQJHPHQW
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A14
A15
A16
BYTE
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
A6
A5
A4
A3
A2
A1
A0
CE
V
SS
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
44-pin SO
21
22
DQ3
DQ11
A10
A11
A12
A13
2RY/BY
3NC
4A7
1NC
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44
WE
A8
A9
RESET
A8 A9
A1
0
A1
1
A1
2
A1
3
A1
4
A1
5
A1
6
BY
T
E
V
SS
DQ
1
5
/A-
1
DQ
7
DQ
1
4
NCNCWE
RE
S
E
T
NCNC
RY
/
B
Y
NC
DQ
2
DQ
1
0
DQ
3
DQ
1
1
V
CC
DQ
4
DQ
1
2
DQ
5
DQ
6
DQ
1
3
1234567891011121314
4847464544434241403938373635
1516
3433
48-pin TSOP
NCA7A6A5A4A3A2A1
A0 CE V
SS
OE DQ
0
DQ
8
DQ
1
DQ
9
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323130292827
2324
2625
AS29F200
AS29
F
200
6HOHFWLRQ#JXLGH
29F200-55 29F200-70 29F200-90 29F200-120 Unit
Maximum access time t
AA
55 70 90 120 ns
Maximum chip enable access time t
CE
55 70 90 120 ns
Maximum output enable access time t
OE
25 30 35 50 ns