APU4003
器件描述：4-BIT MICRO-CONTROLLER WITH LCD DRIVER, 1K WORD
器件厂商：APLUS [Apuls Intergrated Circuits]
文件大小：596.87KB，共9页
Sponsor by e络盟器件资料摘要：
4-Bit Micro-Controller With LCD Driver, 1K Word
Features
y Very low current dissipation
y Wide operating voltage range
y Supports both Ag and Li batteries
y Powerful instruction set
y 4-level subroutine nesting (including interrupt)
y 4 event driven interrupts, 2 external and 2
internal
y ROM size: 1024x15 bits
y RAM size: 64x4 bits
y Input ports: 2 ports/8 pins (S and M)
y Output port: 1 port/4 pins (P)
y Pseudo serial output port (P)
y Input/output ports: 2 ports/8 pins (I/OA and I/OB)
y Control outputs: ALARM, LIGHT
y LCD driver outputs
(can drive up to 75 LCD segments)
y Mask option to select 4 LCD drive modes: static,
duplex (1/2 duty 1/2 bias, 1/3 duty 1/2 bias or 1/3
duty 1/3 bias)
y Mask option permits LCD driver output pins to
be used for DC output ports; up to 25 pins are
available
y Segment PLA circuit permits any layout on LCD
panel
y Built-in clock generator (crystal or RC)
y Built-in voltage doubler, halver, tripler
General Description
The APU4003 is a single chip 4-bit micro-controller with
LCD drivers. It can drive up to 3 common times or 25
segments, i.e. a 75-segment LCD driver. This 4-bit
micro-controller contains a 4-bit parallel processing
ALU, 1024x15-bit program ROM, 64x4-bit data RAM,
input/output ports, alarm driver, timer, clock generator,
crystal and RC oscillator circuit, LCD driver and 79
powerful instructions in a single chip. The HALT
instruction can be used to stop all internal operations
other than timer, clock generator, crystal/RC oscillator
and LCD driver. Very low current dissipation can be
easily achieved by combining 4 kinds of interrupt
functions and HALT instruction to minimize the
operation cycle.
Block Diagram
% L G L U H F W L R Q
, 2 S R U W
2 X W S X W 3 R U W
, 2
$ a
, 2
% a 3 a
$ O D U P
/ L J K W
/ & ' ' U L Y H U
& 2 0 a 6 ( * a 6 ( * 9 6 6 a
6 H J P H Q W 3 / $
% L W ' D W D % X V
5 $ 0 [ % L W V
$ / 8
% L W 3 U H V H W
7 L P H U
, Q V W U X F W L R Q
' H F R G H U
% L W 3 U R J U D P
& R X Q W H U
3 5 2 0
[ % L W
/ H Y H O 6 W D F N
, Q S X W 3 R U W
6 a 0 a
2 V F L O O D W R U
2 6 & , 1
2 6 & 2 8 7
& R Q W U R O
& L U F X L W
5 ( 6 ( 7 , 1 7
& R Q W U R O
& L U F X L W
& 8 3
& 8 3
Preliminary 1 Ver.0.0
Features
y Very low current dissipation
y Wide operating voltage range
y Supports both Ag and Li batteries
y Powerful instruction set
y 4-level subroutine nesting (including interrupt)
y 4 event driven interrupts, 2 external and 2
internal
y ROM size: 1024x15 bits
y RAM size: 64x4 bits
y Input ports: 2 ports/8 pins (S and M)
y Output port: 1 port/4 pins (P)
y Pseudo serial output port (P)
y Input/output ports: 2 ports/8 pins (I/OA and I/OB)
y Control outputs: ALARM, LIGHT
y LCD driver outputs
(can drive up to 75 LCD segments)
y Mask option to select 4 LCD drive modes: static,
duplex (1/2 duty 1/2 bias, 1/3 duty 1/2 bias or 1/3
duty 1/3 bias)
y Mask option permits LCD driver output pins to
be used for DC output ports; up to 25 pins are
available
y Segment PLA circuit permits any layout on LCD
panel
y Built-in clock generator (crystal or RC)
y Built-in voltage doubler, halver, tripler
General Description
The APU4003 is a single chip 4-bit micro-controller with
LCD drivers. It can drive up to 3 common times or 25
segments, i.e. a 75-segment LCD driver. This 4-bit
micro-controller contains a 4-bit parallel processing
ALU, 1024x15-bit program ROM, 64x4-bit data RAM,
input/output ports, alarm driver, timer, clock generator,
crystal and RC oscillator circuit, LCD driver and 79
powerful instructions in a single chip. The HALT
instruction can be used to stop all internal operations
other than timer, clock generator, crystal/RC oscillator
and LCD driver. Very low current dissipation can be
easily achieved by combining 4 kinds of interrupt
functions and HALT instruction to minimize the
operation cycle.
Block Diagram
% L G L U H F W L R Q
, 2 S R U W
2 X W S X W 3 R U W
, 2
$ a
, 2
% a 3 a
$ O D U P
/ L J K W
/ & ' ' U L Y H U
& 2 0 a 6 ( * a 6 ( * 9 6 6 a
6 H J P H Q W 3 / $
% L W ' D W D % X V
5 $ 0 [ % L W V
$ / 8
% L W 3 U H V H W
7 L P H U
, Q V W U X F W L R Q
' H F R G H U
% L W 3 U R J U D P
& R X Q W H U
3 5 2 0
[ % L W
/ H Y H O 6 W D F N
, Q S X W 3 R U W
6 a 0 a
2 V F L O O D W R U
2 6 & , 1
2 6 & 2 8 7
& R Q W U R O
& L U F X L W
5 ( 6 ( 7 , 1 7
& R Q W U R O
& L U F X L W
& 8 3
& 8 3
Preliminary 1 Ver.0.0