AN805
Vishay Siliconix
Document Number: 70649
January 1997
www.vishay.com FaxBack 408-970-5600
1
PWM Optimized Power MOSFETs
for Low-Voltage DC/DC Conversion
Designers of low-voltage dc-to-dc converters have two main
concerns: reducing size and reducing losses. As a way of reducing
size, designers are increasing switching frequencies. But the result
has been reduced converter efficiency. To minimize losses,
MOSFET manufacturers have generally focused on lowering
on-resistance. But the results have not been optimal for dc-to-dc
conversion designs, since gate charge and switching speed issues
have been largely ignored. The dominant losses associated with
MOSFETs were once conduction losses, but this is no longer the
case.
Vishay Siliconix’s new family of PWM optimized MOSFETs has
been designed to give the highest efficiency available for a given
on-resistance in switching applications such as dc-to-dc
conversion. These new devices provide a very low gate charge
per unit of on-resistance, in addition to fast switching times. The
result is reduced gate drive and crossover losses, allowing
designers of dc-to-dc converters to simultaneously reduce the
design footprint and increase efficiency.
MOSFET Losses
A simplistic model of power loss in a MOSFET used in a dc-to-dc
converter (Figure 1) can be calculated if we know the RMS, the
current through the MOSFET, the duty cycle, the gate voltage, and
the r
DS(on)
of the MOSFET. This model can then be used to
compare the efficiency of designs using Vishay Siliconix’s new
PWM optimized MOSFETs versus conventional and low-threshold
power MOSFETs.
The equation that defines the losses associated only with
on-resistance and the gate drive is:
P I
2
RMS r
DS(on)
V
GS
T
J

D Q
g V
GS

V
GS
f (Watts) Eq1
[ ] The value of the parameter before the parenthesis is dependent
on the parameter within the parenthesis.
FIGURE 1. Generic MOSFET model with body diode omitted.
Gate
R
G
Ciss
Crss
I
RMS
C
oss
r
DS(on)
Source
Drain
where:
I
2
RMS The RMS current in the MOSFET (A)
r
DS(on)
On-resistance of the device for a given drive voltage
and junction temperature.
V
GS
The peak driver gate voltage for the MOSFET (V)
[T
J
] Junction temperature of the MOSFET
D Duty factor of the MOSFET (Ratio of on time to off
time)
Q
g
Total gate charge for the MOSFET at a given gate
voltage (C)
f Frequency of MOSFET switching (Hz)
Using Equation 1 we can obtain a plot of power loss (gate loss +
r
DS(on)
loss) as a function of gate voltage at varying switching
frequencies (Figure 2).
[1]
Power Loss (mW)
FIGURE 2. Power loss for PWM optimized Si6801 p-channel
MOSFET as a function of V
GS
and switching
frequency.
0 1 2 3 4 5 6 7
40
30
20
10
0
Si6801 Power Loss, QG, r
DS
V
GS
r
Gate Charge (nC)
V
GS
0.8
0.6
0.4
0.2
0
(
DS(on)
FIGURE 3. Gate losses and on-resistance losses for PWM
optimized power MOSFET (Si6801DQ) versus
conventional (Si6542DQ) and low-threshold
(Si6552DQ) power MOSFETs.
1
V
GS
50
40
30
20
10
Conduction + Gate Charge
Loss (mW)
2 3 4 5 6 7
Technology Comparison: 1 MHz Power Loss

)
40
30
20
10
0