n Block Diagram
AN2018S
Correlated Double Sampling IC
n Overview
The AN2018S is used to reduce noise in CCD im-
age sensor output signal. It performs correlated double-
sampling on image signal sent from a CCD sensor to
output clearer image signal.
n Features
• Operating on low voltage (VCC=4.8V), consuming
little current (ICC=12.7mA typ.)
• Including a high-speed sampling circuit responding
to 510-830H CCD
• 6dB or 9dB fixed gain
• 83-dB high S/N-ratio (at 6dB output)
8765
1234
6dB OUT GND SP1 SP2
9dB OUT BLK SIG.IN VCC
9dB
6dB
S / H
S / H
BLK
BIAS
+
–
50kW
+
–
CDS output (9dB)
Blanking pulse input
CCD signal input
VCC
Sampling pulse input (2)
Sampling pulse input (1)
GND
CDS output (6dB)
Pin No.
1
2
3
4
5
Pin name
6
7
8
pn Pin Descriptions
Unit:mm
6.5– 0.3
4.2– 0.3
0.4
–
0.25
0.4
1.27
0.1
–
0.1
0.15 0.65
1.5
–
0.2
5.0
–
0.3
0.3
8-Pin SOP Package (SOP008-P-0225)