Publication#16235 Rev. C Amendment /0
Issue Date: June 1994
Advanced
Micro
Devices
Am79C940
Media Access Controller for Ethernet (MACE
TM
)
FINAL
DISTINCTIVE CHARACTERISTICS
a73 Integrated Controller with 10BASE-T
transceiver and AUI port
a73 Supports IEEE 802.3/ANSI 8802-3 and Ethernet
standards
a73 84-pin PLCC and 100-pin PQFP Packages
a73 80-pin Thin Quad Flat Pack (TQFP) package
available for space critical applications such
as PCMCIA
a73 Modular architecture allows easy tuning to
specific applications
a73 High speed, 16-bit synchronous host system
interface with 2 or 3 cycles/transfer
a73 Individual transmit (136 byte) and receive (128
byte) FlFOs provide increase of system
latency and support the following features:
– Automatic retransmission with no FIFO
reload
– Automatic receive stripping and transmit
padding (individually programmable)
– Automatic runt packet rejection
– Automatic deletion of collision frames
– Automatic retransmission with no FIFO
reload
a73 Direct slave access to all on board
configuration/status registers and transmit/
receive FlFOs
a73 Direct FIFO read/write access for simple
interface to DMA controllers or l/O processors
a73 Arbitrary byte alignment and little/big endian
memory interface supported
a73 Internal/external loopback capabilities
a73 External Address Detection Interface (EADI )
for external hardware address filtering in
bridge/router applications
a73 JTAG Boundary Scan (IEEE 1149.1 ) test
access port interface for board level
production test
a73 Integrated Manchester Encoder/Decoder
a73 Digital Attachment Interface (DAI ) allows
by-passing of differential Attachment Unit
Interface (AUI)
a73 Supports the following types of network
interface:
– AUI to external 10BASE2, 10BASE5 or
10BASE-F MAU
– DAI port to external 10BASE2, 10BASE5,
10BASE-T, 10BASE-F MAU
– General Purpose Serial Interface (GPSI) to
external encoding/decoding scheme
– Internal 10BASE-T transceiver with
automatic selection of 10BASE-T or AUI port
a73 Sleep mode allows reduced power consump-
tion for critical battery powered applications
a73 1 MHz – 25 MHz system clock speed
GENERAL DESCRIPTION
The Media Access Controller for Ethernet (MACE) chip
is a CMOS VLSI device designed to provide flexibility in
customized LAN design. The MACE device is specifi-
cally designed to address applications where multiple
I/O peripherals are present, and a centralized or system
specific DMA is required. The high speed, 16-bit syn-
chronous system interface is optimized for an external
DMA or I/O processor system, and is similar to many ex-
isting peripheral devices, such as SCSI and serial
link controllers.
The MACE device is a slave register based peripheral.
All transfers to and from the system are performed using
simple memory or I/O read and write commands. In con-
junction with a user defined DMA engine, the MACE
chip provides an IEEE 802.3 interface tailored to a
specific application. Its superior modular architecture
and versatile system interface allow the MACE device to
be configured as a stand-alone device or as a connec-
tivity cell incorporated into a larger, integrated system.
The MACE device provides a complete Ethernet node
solution with an integrated 10BASE-T transceiver, and
supports up to 25-MHz system clocks. The MACE de-
vice embodies the Media Access Control (MAC) and
Physical Signaling (PLS) sub-layers of the IEEE 802.3
standard, and provides an IEEE defined Attachment
Unit Interface (AUI) for coupling to an external Medium
Attachment Unit (MAU). The MACE device is
compliant with 10BASE2, 10BASE5, 10BASE-T, and
10BASE-F transceivers.