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Publication# 17348 Rev. B Amendment /0
Issue Date: May 1993
Advanced
Micro
Devices
Am53CF94/Am53CF96
Enhanced SCSI-2 Controller (ESC)
PRELIMINARY
DISTINCTIVE CHARACTERISTICS
a73 Pin/function compatible with Emulex
FAS216/236
a73 AMD’s Patented programmable GLITCH
EATER
TM
Circuitry on REQ and ACK inputs
a73 10 Mbytes/s synchronous Fast SCSI transfer
rate
a73 20 Mbytes/s DMA transfer rate
a73 16-Bit DMA interface plus 2 bits of parity
a73 Flexible three bus architecture
a73 Single-ended SCSI bus supported by
Am53CF94
a73 Differential SCSI bus supported by Am53CF96
a73 Selection of multiplexed or non-multiplexed
address and data bus
a73 High current drivers (48 mA) for direct
connection to the single-ended SCSI bus
a73 Supports Disconnect and Reselect commands
a73 Supports burst mode DMA operation with a
threshold of eight
a73 Supports 3-byte tagged-queueing as per the
SCSI-2 specification
a73 Supports group 2 and 5 command recognition
as per the SCSI-2 specification
a73 Advanced CMOS process for lower power
consumption
a73 AMD’s exclusive programmable power-down
feature
a73 24-Bit extended transfer counter allows for
data block transfer of up to 16 Mbytes
a73 Independently programmable 3-byte message
and group 2 identification
a73 Additional check for ID message during
bus-initiated Select with ATN
a73 Reselection has QTAG features of ATN3
a73 Access FIFO Command
a73 Delayed enable signal for differential drivers
avoid contention on SCSI differential lines
a73 Programmable Active Negation on REQ, ACK
and Data lines
a73 Register programmable control of assertion/
deassertion delay for REQ and ACK lines
a73 Part-unique ID code
a73 Am53CF94 available in 84-pin PLCC package
a73 Am53CF96 available in 100-pin PQFP package
a73 Am53CF94 available in 3.3 V version
a73 Supports clock operating frequencies from
10 MHz–40 MHz
a73 Supports Scatter-Gather or Back-to-Back
synchronous data transfers
GENERAL DESCRIPTION
The Enhanced SCSI-2 Controller (ESC) was designed
to support Fast SCSI-2 transfer rates of up to
10 Mbytes/s in synchronous mode and up to 7 Mbytes/s
in the asynchronous mode. The ESC is downward com-
patible with the Am53C94/96, combining its functionality
with features such as Fast SCSI, programmable Active
Negation, a 24-bit transfer counter, and a part-unique ID
code containing manufacturer and serial # information.
AMD’s proprietary features such as power-down mode
for SCSI transceivers, programmable GLITCH EATER,
and extended Target command set are also included for
improved product performance.
The Enhanced SCSI-2 Controller (ESC) has a flexible
three bus architecture. The ESC has a 16-bit DMA inter-
face, an 8-bit host data interface and an 8-bit SCSI data
interface. The ESC is designed to minimize host inter-
vention by implementing common SCSI sequences in
hardware. An on-chip state machine reduces protocol
overheads by performing the required sequences in re-
sponse to a single command from the host. Selection,
reselection, information transfer and disconnection
commands are directly supported.
The 16-byte-internal FIFO further assists in minimizing
host involvement. The FIFO provides a temporary stor-
age for all command, data, status and message bytes as
they are transferred between the 16-bit host data bus
and the 8-bit SCSI data bus. During DMA operations the
FIFO acts as a buffer to allow greater latency in the DMA
channel. This permits the DMA channel to be sus-
pended for higher priority operations such as DRAM re-
fresh or reception of an ISDN packet.
Parity on the DMA bus is optional. Parity can either be
generated and checked or it can be simply passed
through.
The Target command set for the Am53CF94/96 in-
cludes an additional command, the Access FIFO com-
mand, to allow the host or DMA controller to remove re-
maining FIFO data following the host’s issuance of a
Target abort DMA command or following an abort due to