© 2005 Fairchild Semiconductor Corporation DS012446 www.fairchildsemi.com
January 1999
Revised June 2005
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62245
• 74L
VTH162245 Low
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ceiver

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25
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A Port

Out
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74LVT162245 74LVTH162245
Low Voltage 16-Bit Transceiver with 3-STATE Outputs
and 25G58 Series Resistors in A Port Outputs
General Description
The LVT162245 and LVTH162245 contains sixteen non-
inverting bidirectional buffers with 3-STATE outputs and is
intended for bus oriented applications. The device is byte
controlled. Each byte has separate control inputs which
can be shorted together for full 16-bit operation. The T/R
inputs determine the direction of data flow through the
device. The OE inputs disable both the A and B ports by
placing them in a high impedance state.
The LVT162245 and LVTH162245 are designed with
equivalent 25c58 series resistance in both the HIGH and
LOW states on the A Port outputs. This design reduces line
noise in applications such as memory address drivers,
clock drivers, and bus transceivers/transmitters.
The LVTH162245 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These non-inverting transceivers are designed for low volt-
age (3.3V) V
CC
applications, but with the capability to pro-
vide a TTL interface to a 5V environment. The LVT162245
and LVTH162245 are fabricated with an advanced
BiCMOS technology to achieve high speed operation simi-
lar to 5V ABT while maintaining a low power dissipation.
Features
a73 Input and output interface capability to systems at
5V V
CC
a73 Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs (74LVTH162245),
also available without bushold feature (74LVT162245).
a73 Live insertion/extraction permitted
a73 Power Up/Down high impedance provides glitch-free
bus loading
a73 A Port outputs include equivalent series resistance of
25c58 making external termination resistors unnecessary
and reducing overshoot and undershoot
a73 A Port outputs source/sink c11412 mA.
B Port outputs source/sink c1632 mA/c1464 mA
a73 Functionally compatible with the 74 series 162245
a73 Latch-up performance exceeds 500 mA
a73 ESD performance:
Human-body model c33 2000V
Machine model c33 200V
Charged-device model c33 1000V
a73 Also packaged in plastic Fine Pitch Ball Grid Array
(FBGA)

Ordering Code:
Note 1: Ordering code “G” indicates Trays.
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number Package Number Package Description
74LVT162245G
(Note 1)(Note 2)
BGA54A
(Preliminary)
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74LVT162245MEA
(Note 2)
MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVT162245MTD
(Note 2)
MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH162245G
(Note 1)(Note 2)
BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74LVTH162245MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TUBE]
74LVTH162245MEX MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TAPE and REEL]
74LVTH162245MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TUBE]
74LVTH162245MTX MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]