FINAL
Publication# 18880 Rev: C Amendment/+2
Issue Date: April 1998
Am28F512A
512 Kilobit (64 K x 8-Bit)
CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms
DISTINCTIVE CHARACTERISTICS
a73 High performance
— 70 ns maximum access time
a73 CMOS low power consumption
— 30 mA maximum active current
— 100 µA maximum standby current
— No data retention power consumption
a73 Compatible with JEDEC-standard byte-wide
32-Pin EPROM pinouts
— 32-pin PDIP
— 32-pin PLCC
— 32-pin TSOP
a73 100,000 write/erase cycles minimum
a73 Write and erase voltage 12.0 V −5%
a73 Latch-up protected to 100 mA from -1 V
to V
CC
+1 V
a73 Embedded Erase Electrical Bulk Chip-Erase
— Two seconds typical chip-erase including
pre-programming
a73 Embedded

Program
— 4 µs typical byte-program including time-out
— One second typical chip program
a73 Command register architecture for
microprocessor/microcontroller compatible
write interface
a73 On-chip address and data latches
a73 Advanced CMOS flash memory technology
— Low cost single transistor memory cell
a73 Embedded

algorithms for completely
self-timed write/erase operations
GENERAL DESCRIPTION
The Am28F512A is a 512 Kbit Flash memory orga-
nized as 64 Kbytes of 8 bits each. AMD’s Flash memo-
ries offer the most cost-effective and reliable read/write
non- volatile random access memory. The Am28F512A
is packaged in 32-pin PDIP, PLCC, and TSOP versions.
It is designed to be reprogrammed and erased in-sys-
tem or in standard EPROM programmers. The
Am28F512A is erased when shipped from the factory.
The standard Am28F512A offers access times as fast
as 70 ns, allowing operation of high-speed micropro-
cessors without wait states. To eliminate bus conten-
tion, the Am28F512A has separate chip enable (CE#)
and output enable (OE#) controls.
AMD’s Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
Am28F512A uses a command register to manage this
functionality, while maintaining a JEDEC Flash stan-
dard 32-pin pinout. The command register allows for
100% TTL level control inputs and fixed power supply
levels during erase and programming.
AMD’s Flash technology reliably stores memory con-
tents even after 100,000 erase and program cycles.
The AMD cell is designed to optimize the erase and
programming mechanisms. In addition, the combina-
tion of advanced tunnel oxide processing and low inter-
nal electric fields for erase and programming
operations produces reliable cycling. The Am28F512A
uses a 12.0V±5% V
PP
high voltage input to perform
the erase

and programming functions.
The highest degree of latch-up protection is achieved
with AMD’s proprietary non-epi process. Latch-up pro-
tection is provided for stresses up to 100 milliamps on
address and data pins from –1 V to V
CC
+1 V.
Embedded Program
The Am28F512A is byte programmable using the Em-
bedded Programming algorithm. The Embedded Pro-
gramming algorithm does not require the system to
time-out or verify the data programmed. The typical
room temperature programming time of the
Am28F512A is one second.
Embedded Erase
The entire chip is bulk erased using the Embedded
Erase algorithm. The Embedded

Erase algorithm auto-
matically programs the entire array prior to electrical
erase. The timing and verification of electrical erase are