4-281
March 1997
82C83H
CMOS Octal Latching Inverting Bus Driver
Features
• Full 8-Bit Parallel Latching Buffer
• Bipolar 8283 Compatible
• Three-State Inverting Outputs
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . . 25ns Max
• Gated Inputs
- Reduce Operating Power
- Eliminate the Need for Pull-Up Resistors
• Single 5V Power Supply
• Low Power Operation
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
• Operating Temperature Ranges
- C82C83H . . . . . . . . . . . . . . . . . . . . . . . . .0
o
C to +70
o
C
- I82C83H . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
- M82C83H . . . . . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Description
The Intersil 82C83H is a high performance CMOS Octal
Latching Buffer manufactured using a self-aligned silicon gate
CMOS process (Scaled SAJI IV). The 82C83H provides an 8-
bit parallel latch/buffer in a 20 lead pin package. The active
high strobe (STB) input allows transparent transfer of data
and latches data on the negative transition of this signal. The
active low output enable (OE) permits simple interface to
microprocessor systems. The 82C83H provides inverted data
at the outputs.
Pinouts
82C83H (PDIP, CERDIP)
TOP VIEW
82C83H (PLCC, CLCC)
TOP VIEW
Ordering Information
PART NO. PACKAGE TEMP RANGE PKG. NO
CP82C83H 20 Ld PDIP 0
o
C to +70
o
C E20.3
IP82C83H -40
o
C to +85
o
C E20.3
CS82C83H 20 Ld PLCC 0
o
C to +70
o
C N20.35
IS82C83H -40
o
C to +85
o
C N20.35
CD82C83H 20 Ld CERDIP 0
o
C to +70
o
C F20.3
ID82C83H -40
o
C to +85
o
C F20.3
MD82C83H/B 0
o
C to +70
o
C F20.3
8406702RA SMD# -55
o
C to +125
o
C F20.3
MR82C83H/B 20 Pad CLCC -55
o
C to +125
o
C J20.A
84067022A SMD# -55
o
C to +125
o
C J20.A
TRUTH TABLE
STB OE DI DO
X H X HI-Z
HLLH
HLHL
↓ LX†
H = Logic One
L = Logic Zero
X = Don‘t Care
HI-Z = High Impedance
↓ = Negative Transition
† = Latched to Value of Last
Data
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1DI
0
DI
1
DI
2
DI
3
DI
4
DI
5
DI
7
DI
6
OE
GND
V
CC
DO
1
DO
2
DO
3
DO
0
DO
4
DO
5
DO
6
DO
7
STB
PIN NAMES
PIN DESCRIPTION
DI
0
- DI
7
Data Input Pins
DO
0
- DO
7
Data Output Pins
STB Active High Strobe
OE Active Low Output Enable
193 2 201
15
16
17
18
14
9 10 11 12 13
4
5
6
7
8
DI
4
DI
5
DI
6
DI
7
DI
3
OE GND STB DO
7
DO
6
DO
2
DO
3
DO
4
DO
5
DO
1
DI
2
DI
1
DI
0
V
CC
DO
0
File Number 2971.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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