REV. B
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a
ADSP-21065L
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2000
DSP Microcomputer
SUMMARY
High Performance Signal Computer for Communica-
tions, Audio, Automotive, Instrumentation and
Industrial Applications
Super Harvard Architecture Computer (SHARC
®
)
Four Independent Buses for Dual Data, Instruction,
and I/O Fetch on a Single Cycle
32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit Floating-
Point Arithmetic
544 Kbits On-Chip SRAM Memory and Integrated I/O
Peripheral
I
2
S Support, for Eight Simultaneous Receive and Trans-
mit Channels
KEY FEATURES
66 MIPS, 198 MFLOPS Peak, 132 MFLOPS Sustained
Performance
User-Configurable 544 Kbits On-Chip SRAM Memory
Two External Port, DMA Channels and Eight Serial
Port, DMA Channels
SDRAM Controller for Glueless Interface to Low Cost
External Memory (@ 66 MHz)
64M Words External Address Range
12 Programmable I/O Pins and Two Timers with Event
Capture Options
Code-Compatible with ADSP-2106x Family
208-Lead MQFP or 196-Ball Mini-BGA Package
3.3 Volt Operation
Flexible Data Formats and 40-Bit Extended Precision
32-Bit Single-Precision and 40-Bit Extended-Precision IEEE
Floating-PointData Formats
32-Bit Fixed-Point Data Format, Integer and Fractional,
with Dual 80-Bit Accumulators
Parallel Computations
Single-Cycle Multiply and ALU Operations in Parallel with
Dual Memory Read/Writes and Instruction Fetch
Multiply with Add and Subtract for Accelerated FFT But-
terfly Computation
1024-Point Complex FFT Benchmark: 0.274 ms (18,221
Cycles)
SPORT 1
4
IOP
REGISTERS
(MEMORY MAPPED)
CONTROL,
STATUS, TIMER
&
DATA BUFFERS
I/O PROCESSOR
INSTRUCTION
CACHE
32 H11547 48 BIT
DATA ADDR
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT I/O PORT
BLOCK 0
BLOCK 1
JTAG
TEST &
EMULATION
7
HOST PORT
ADDR BUS
MUX
IOA
17
IOD
48
MULTIPROCESSOR
INTERFACE
DUAL-PORTED SRAM
EXTERNAL
PORT
DATA BUS
MUX
32
24
24 PM ADDRESS BUS
DM ADDRESS BUS
PM DATA BUS
DM DATA BUS
BUS
CONNECT
(PX)
DATA
REGISTER
FILE
16 H11547 40 BIT
BARREL
SHIFTER
ALUMULTIPLIER
32
48
40
CORE PROCESSOR
DMA
CONTROLLER
PROGRAM
SEQUENCER
DAG2
8 H11547 4 H11547 24
SDRAM
INTERFACE
(I
2
S)
(2 Rx, 2Tx)
(2 Rx, 2Tx)
(I
2
S)
SPORT 0
DAG1
8 H11547 4 H11547 32
DATA DATA
DATA
ADDR
ADDR
ADDR
Figure 1. Functional Block Diagram
SHARC is a registered trademark of Analog Devices, Inc.