A-Data ADS8608A8A
Synchronous DRAM 8M x 8 Bit x 4 Banks

General Description
The ADS8608A8A are four-bank Synchronous
DRAMs organized as 8,388,608 words x 8 bits x 4
banks.
Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clock cycle.
Range of operating frequencies, programmable
burst length and programmable latencies allow the
same device to be useful for a variety of high
bandwidth high performance memory system
applications

Features
•JEDEC standard LVTTL 3.3V power supply
•MRS Cycle with address key programs
-CAS Latency (2 & 3)
-Burst Length (1,2,4,8,& full page)
-Burst Type (sequential & Interleave)
•4 banks operation
•All inputs are sampled at the positive edge of
the system clock
•Burst Read single write operation
•Auto & Self refresh
•DQM for masking
•8192 Refresh Cycles
•Package:54-pins 400 mil TSOP-Type II
Ordering Information.
Part No. Frequency Interface Package
ADS8608A8A-75 133Mhz-333 LVTTL 400mil 54pin TSOPII
ADS8608A8A-75A 133Mhz-222 LVTTL 400mil 54pin TSOPII
Pin Assignment
54
53
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28
52
51
50
49
48
47
46
45
44
43
36
37
35
34
33
41
42
40
39
38
32
31
30
29
Vss
DQ7
VssQ
NC
DQ6
VCCQ
NC
DQ5
VSSQ
NC
DQ4
VCCQ
NC
VSS
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VCC
DQ0
VCCQ
NC
DQ1
VSSQ
NC
DQ2
VCCQ
NC
DQ3
VSSQ
NC
VCC
NC
/WE
/CAS
/RAS
/CS
BS0
BS1
A10/AP
A0
A1
A2
A3
VCC
54-pin plastic TSOP II 400 mil
Rev 1.0 December, 2001 1