A-Data ADS4616A4A
Synchronous DRAM 512K x 16 Bit x 2 Banks

General Description
The ADS4616A4A are two-bank Synchronous
DRAMs organized as 524,288 words x 16 bits x 2
banks,
Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clock cycle.
Range of operating frequencies, programmable
burst length and programmable latencies allow the
same device to be useful for a variety of high
bandwidth high performance memory system
applications

Features
•Single 3.3V +/- 0.3V power supply
•MRS Cycle with address key programs
-CAS Latency (2 & 3)
-Burst Length (1,2,4,8, & full page)
-Burst Type (sequential & Interleave)
•2 banks operation
•All inputs are sampled at the positive edge of
the system clock
•Burst Read single write operation
•Auto & Self refresh
•4096 refresh cycle
•DQM for masking
•Package:50-pins 400 mil TSOP-Type II
Ordering Information.
Part No. Frequency Interface Package
ADS4616A4A-5 200Mhz LVTTL 400mil 50pin TSOPII
ADS4616A4A -6 166Mhz LVTTL 400mil 50pin TSOPII
ADS4616A4A -7 143Mhz LVTTL 400mil 50pin TSOPII
Pin Assignment
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25 26
27
28
50
49
48
47
46
45
44
43
36
37
35
34
33
41
42
40
39
38
32
31
30
29
Vss
DQ15
VssQ
DQ14
DQ13
VDD Q
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
DDQ
DQ8
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
LDQM
/WE
/CAS
/RAS
/CS
A10
A0
A1
A2
A3
(BS)A11
DDV
50-pin plastic TSOP II 400 mil

Rev 1 December, 2001 1