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ADM9690AR

器件描述:Power Supply and Watchdog Timer Monitoring Circuit
器件厂商:AD [Analog Devices]
厂商主页:http://www.analog.com/
文件大小:76.37KB,共6页
Sponsor by e络盟
器件资料摘要:
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
ADM9690
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2000
Power Supply and Watchdog Timer
Monitoring Circuit
FUNCTIONAL BLOCK DIAGRAM
WATCHDOG
TRANSITION
DETECTOR
V
CC
V
MON
OSC SEL1
OSC SEL2
RESET(2)
TIMER
RESET(1)
TIMER
4.31V
ADM9690
RESET(1)
RESET(2)
WATCHDOG
INPUT (WDI)
GND
WATCHDOG
TIMEBASE
FEATURES
Precision Voltage Monitor (4.31 V)
Watchdog Timeout Monitor
Selectable Watchdog Timeout—0.75 ms, 1.5 ms,
12.5 ms, 25 ms
Two RESET Outputs
APPLICATIONS
Microprocessor Systems
Computers
Printers
Controllers
Intelligent Instruments
GENERAL DESCRIPTION
The ADM9690 contains a voltage monitoring comparator and a
watchdog timer monitor. It is designed to monitor the 5 V
power supply to a microprocessor and the microprocessor opera-
tion via a watchdog function.
The voltage monitoring comparator monitors the voltage on
V
MON
. If it drops outside tolerance, as will happen during a
power-fail, two reset signals are generated. Both reset signals go
active (low) simultaneously. They will remain active while
V
MON
is below the threshold, and for 50 ms (RESET(1)) or
60 ms (RESET(2)) after V
MON
climbs above the reset thresh-
old. RESET(1) is intended to provide a power-on reset signal
for the µP while RESET(2) is used to hold additional circuitry
in a reset state until the µP has regained control following a
power-up. The voltage monitoring circuitry remains operational
with V
CC
as low as 2 V.
The watchdog timer monitoring circuit is designed to monitor
the activity on the WDI input. This input is normally connected
to an output line on the µP. Its function is to check that the
microprocessor has not stalled in an infinite loop. If there is a
period of inactivity for the watchdog timeout period, both reset
outputs are activated. As above, RESET(1) remains low for
50 ms while RESET(2) remains low for an additional 10 ms.
The watchdog timer is restarted when RESET(1) goes inactive.
The actual watchdog timeout period is adjustable using two
select inputs SEL1 and SEL2.
The ADM9690 is available in an 8-lead SOIC package. It is
specified over the industrial temperature range.