ADC12451
器件描述：Dynamically-Tested Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold
器件厂商：NSC [National Semiconductor]
文件大小：311.43KB，共18页
Sponsor by e络盟器件资料摘要：
TL/H/11025
ADC12451
Dynamically-Tested
Self-Calibrating
12-Bit
Plus
Sign
A/D
Converter
with
Sample-and-Hold
December 1994
ADC12451 Dynamically-Tested Self-Calibrating
12-Bit Plus Sign A/D Converter with Sample-and-Hold
General Description
The ADC12451 is a CMOS 12-bit plus sign successive ap-
proximation analog-to-digital converter whose dynamic
specifications (S/N, THD, etc.) are tested and guaranteed.
On request, the ADC12451 goes through a self-calibration
cycle that adjusts linearity, zero and full-scale errors. The
ADC12451 also has the ability to go through an Auto-Zero
cycle that corrects the zero error during every conversion.
The analog input to the ADC12451 is tracked and held by
the internal circuitry, so an external sample-and-hold is not
required. The ADC12451 has a S/H control input which di-
rectly controls the track-and-hold state of the A/D. A unipo-
lar analog input voltage range (0V to a5V) or a bipolar
range (b5V to a5V) can be accommodated with g5V sup-
plies.
The 13-bit data result is available on the eight outputs of the
ADC12451 in two bytes, high-byte first and sign extended.
The digital inputs and outputs are compatible with TTL or
CMOS logic levels.
Applications
Y
Digital Signal Processing
Y
Audio
Y
Telecommunications
Y
High Resolution Process Control
Y
Instrumentation
Features
Y
Self-calibration provides excellent temperature stability
Y
Internal sample-and-hold
Y
8-bit mP/DSP interface
Y
Bipolar input range with a single a5V reference
Key Specifications
Y
Resolution 12 bits plus sign
Y
Conversion Time 7.7 ms (max)
Y
Sampling Rate 83 kHz (max)
Y
Bipolar Signal/Noise 73.5 dB (min)
Y
Total Harmonic Distortion b78.0 dB (max)
Y
Aperture Time 100 ns
Y
Aperture Jitter 100 ps
rms
Y
Zero Error g2 LSB (max)
Y
Positive Full-Scale Error g1.5 LSB (max)
Y
Power Consumption
@
g5V 113 mW (max)
Simplified Block Diagram
TL/H/11025–1
Connection Diagram
Dual-In-Line Package
TL/H/11025–2
Top View
Ordering Information
Industrial
Package
(b40§C
s
T
A
s
85§C)
ADC12451CIJ J24A
Military
Package
(b55§C
s
T
A
s
125§C)
ADC12451CMJ,
J24A
ADC12451CMJ/883
TRI-STATE is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.
ADC12451
Dynamically-Tested
Self-Calibrating
12-Bit
Plus
Sign
A/D
Converter
with
Sample-and-Hold
December 1994
ADC12451 Dynamically-Tested Self-Calibrating
12-Bit Plus Sign A/D Converter with Sample-and-Hold
General Description
The ADC12451 is a CMOS 12-bit plus sign successive ap-
proximation analog-to-digital converter whose dynamic
specifications (S/N, THD, etc.) are tested and guaranteed.
On request, the ADC12451 goes through a self-calibration
cycle that adjusts linearity, zero and full-scale errors. The
ADC12451 also has the ability to go through an Auto-Zero
cycle that corrects the zero error during every conversion.
The analog input to the ADC12451 is tracked and held by
the internal circuitry, so an external sample-and-hold is not
required. The ADC12451 has a S/H control input which di-
rectly controls the track-and-hold state of the A/D. A unipo-
lar analog input voltage range (0V to a5V) or a bipolar
range (b5V to a5V) can be accommodated with g5V sup-
plies.
The 13-bit data result is available on the eight outputs of the
ADC12451 in two bytes, high-byte first and sign extended.
The digital inputs and outputs are compatible with TTL or
CMOS logic levels.
Applications
Y
Digital Signal Processing
Y
Audio
Y
Telecommunications
Y
High Resolution Process Control
Y
Instrumentation
Features
Y
Self-calibration provides excellent temperature stability
Y
Internal sample-and-hold
Y
8-bit mP/DSP interface
Y
Bipolar input range with a single a5V reference
Key Specifications
Y
Resolution 12 bits plus sign
Y
Conversion Time 7.7 ms (max)
Y
Sampling Rate 83 kHz (max)
Y
Bipolar Signal/Noise 73.5 dB (min)
Y
Total Harmonic Distortion b78.0 dB (max)
Y
Aperture Time 100 ns
Y
Aperture Jitter 100 ps
rms
Y
Zero Error g2 LSB (max)
Y
Positive Full-Scale Error g1.5 LSB (max)
Y
Power Consumption
@
g5V 113 mW (max)
Simplified Block Diagram
TL/H/11025–1
Connection Diagram
Dual-In-Line Package
TL/H/11025–2
Top View
Ordering Information
Industrial
Package
(b40§C
s
T
A
s
85§C)
ADC12451CIJ J24A
Military
Package
(b55§C
s
T
A
s
125§C)
ADC12451CMJ,
J24A
ADC12451CMJ/883
TRI-STATE is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.