AD9958
器件描述：2-Channel 500 MSPS DDS with 10-Bit DACs
器件厂商：AD [Analog Devices]
文件大小：1051.24KB，共40页
Sponsor by e络盟器件资料摘要：
2-Channel 500 MSPS DDS
with 10-Bit DACs
AD9958
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
2 synchronized DDS channels @ 500 MSPS
Independent frequency/phase/amplitude control between
channels
Matched latencies for frequency/phase/amplitude changes
Excellent channel-to-channel isolation (>72 dB)
Linear frequency/phase/amplitude sweeping capability
Up to 16 levels of frequency/phase/amplitude modulation
(pin-selectable)
2 integrated 10-bit D/A converters (DACs)
Individually programmable DAC full-scale currents
32-bit frequency tuning resolution
14-bit phase offset resolution
10-bit output amplitude scaling resolution
Serial I/O Port (SPI) with 800Mbps data throughput
Software-/hardware-controlled power-down
Dual supply operation (1.8 V DDS core/3.3 V serial I/O)
Multiple device synchronization
Selectable 4× to 20× REF_CLK multiplier (PLL)
Selectable REF_CLK crystal oscillator
56-Lead LFCSP
APPLICATIONS
Agile local oscillator
Phased array radar/sonar
Instrumentation
Synchronized clocking
RF source for AOTF
Single-side band suppressed carrier
Quadrature communications
FUNCTIONAL BLOCK DIAGRAM
AD9958
32 32 1015
IOUT
10
Σ Σ Σ
DAC
COS(X)
DDS CORE
IOUT
32
∆FTW
FTW
SYNC_CLK
CLK_MODE_SEL
BUFFER/
XTAL
OSCILLATOR
SYSTEM
CLK
1.8V
AVDD DVDD
SYNC_IN
SYNC_OUT
I/O_UPDATE
32
32 PHASE/
∆PHASE
AMP/
∆AMP
1014
1015
IOUT
10
Σ Σ Σ
DAC
IOUT
DAC_RSET
REF_CLK
REF_CLK
PWR_DWN_CTL
MASTER_RESET
SCLK
SDIO_0
SDIO_1
SDIO_2
SDIO_3
CS
TIMING AND CONTROL LOGIC
SCALABLE
DAC REF
CURRENT
MUX
I/O
PORT
BUFFER
CONTROL
REGISTERS
CHANNEL
REGISTERS
PROFILE
REGISTERS
÷4
REF CLOCK
MULTIPLIER
4× TO 20×
1.8V
PS0 PS1 PS2 PS3 DVDD_I/O
COS(X)
DDS CORE
05252-001
Figure 1.
with 10-Bit DACs
AD9958
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
2 synchronized DDS channels @ 500 MSPS
Independent frequency/phase/amplitude control between
channels
Matched latencies for frequency/phase/amplitude changes
Excellent channel-to-channel isolation (>72 dB)
Linear frequency/phase/amplitude sweeping capability
Up to 16 levels of frequency/phase/amplitude modulation
(pin-selectable)
2 integrated 10-bit D/A converters (DACs)
Individually programmable DAC full-scale currents
32-bit frequency tuning resolution
14-bit phase offset resolution
10-bit output amplitude scaling resolution
Serial I/O Port (SPI) with 800Mbps data throughput
Software-/hardware-controlled power-down
Dual supply operation (1.8 V DDS core/3.3 V serial I/O)
Multiple device synchronization
Selectable 4× to 20× REF_CLK multiplier (PLL)
Selectable REF_CLK crystal oscillator
56-Lead LFCSP
APPLICATIONS
Agile local oscillator
Phased array radar/sonar
Instrumentation
Synchronized clocking
RF source for AOTF
Single-side band suppressed carrier
Quadrature communications
FUNCTIONAL BLOCK DIAGRAM
AD9958
32 32 1015
IOUT
10
Σ Σ Σ
DAC
COS(X)
DDS CORE
IOUT
32
∆FTW
FTW
SYNC_CLK
CLK_MODE_SEL
BUFFER/
XTAL
OSCILLATOR
SYSTEM
CLK
1.8V
AVDD DVDD
SYNC_IN
SYNC_OUT
I/O_UPDATE
32
32 PHASE/
∆PHASE
AMP/
∆AMP
1014
1015
IOUT
10
Σ Σ Σ
DAC
IOUT
DAC_RSET
REF_CLK
REF_CLK
PWR_DWN_CTL
MASTER_RESET
SCLK
SDIO_0
SDIO_1
SDIO_2
SDIO_3
CS
TIMING AND CONTROL LOGIC
SCALABLE
DAC REF
CURRENT
MUX
I/O
PORT
BUFFER
CONTROL
REGISTERS
CHANNEL
REGISTERS
PROFILE
REGISTERS
÷4
REF CLOCK
MULTIPLIER
4× TO 20×
1.8V
PS0 PS1 PS2 PS3 DVDD_I/O
COS(X)
DDS CORE
05252-001
Figure 1.