EEWorld首页 新闻 论坛 博客 白皮书 专题 电子电路 电子器件 单片机 嵌入式 模拟电路 DSP FPGA 电源管理 手机/便携 医疗电子 汽车电子 工业控制
厂商索引:A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-S-T-U-V-W-X-Y-Z

AD9218

器件描述:10-Bit, 40/65/80/105 MSPS 3 V Dual A/D Converter
器件厂商:AD [Analog Devices]
厂商主页:http://www.analog.com/
文件大小:1591.26KB,共24页
Sponsor by e络盟
器件资料摘要:
REV.0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
AD9218
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2001
FUNCTIONAL BLOCK DIAGRAM
10-Bit, 40/65/80/105 MSPS
3 V Dual A/D Converter
TIMING
ADC
OUTPUT
REGISTER
REF
T/H
10 10
ADC
OUTPUT
REGISTER
T/H
10 10
TIMING
USER
SELECT #1
USER
SELECT #2
DATA
FORMAT/
GAIN
D
9B
–D
0B
D
9A
–D
0A
V
DD
GNDV
D
AD9218ENCODE A
ENCODE B
A
IN
B
A
IN
A
A
IN
A
REF
IN
A
REF
IN
B
REF
OUT
A
IN
B
FEATURES
Dual 10-Bit, 40 MSPS, 65 MSPS, 80 MSPS, and
105MSPS ADC
Low Power: 275 mW at 105 MSPS per Channel
On-Chip Reference and Track/Holds
300 MHz Analog Bandwidth Each Channel
SNR = 57 dB @ 41 MHz, Encode = 80 MSPS
1 V p-p or 2 V p-p Analog Input Range Each Channel
Single 3.0 V Supply Operation (2.7 V–3.6 V)
Power-Down Mode for Single Channel Operation
Two’s Complement or Offset Binary Output Mode
Output Data Alignment Mode
Pin-Compatible with 8-Bit AD9288
–75 dBc Crosstalk between Channels
APPLICATIONS
Battery-Powered Instruments
Hand-Held Scopemeters
Low Cost Digital Oscilloscopes
I and Q Communications
Ultrasound Equipment
GENERAL DESCRIPTION
The AD9218 is a dual 10-bit monolithic sampling analog-to-
digital converter with on-chip track-and-hold circuits and is
optimized for low cost, low power, small size and ease of use.
The product operates at a 105 MSPS conversion rate with
outstanding dynamic performance over its full operating range.
Each channel can be operated independently.
The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power
supply and an encode clock for full operation. No external
reference or driver components are required for many applica-
tions. The digital outputs are TTL/CMOS-compatible and a
separate output power supply pin supports interfacing with
3.3 V or 2.5 V logic.
The clock input is TTL/CMOS-compatible and the 10-bit
digital outputs can be operated from 3.0 V (2.5 V to 3.6 V)
supplies. User-selectable options are available to offer a combi-
nation of power-down modes, digital data formats and digital
data timing schemes. In power-down mode, the digital outputs
are driven to a high-impedance state.
Fabricated on an advanced CMOS process, the AD9218 is
available in a 48-lead surface-mount plastic package (7 × 7 mm
LQFP) specified over the industrial temperature range (–40°C
to +85°C).
PRODUCT HIGHLIGHTS
Low Power—Just 275 mW power dissipation per channel at
105 MSPS. Other speed grade proportionally scaled down while
maintaining high ac performance.
Pin Compatibility Upgrade—Allows easy migration from 8-bit
to 10-bit. Pin-compatible with the 8-bit AD9288 dual ADC.
Ease of Use—On-chip reference and user controls provide flex-
ibility in system design.
High Performance—Maintain 54 dB SNR at 105 MSPS with a
Nyquist input.
Channel Crosstalk—Very low at –75 dBc.