FEATURES
eroflex Circuit Technology - Advanced Multichip Modules © SCD1663 REV A 4/28/98
CIRCUIT TECHNOLOGY
www.aeroflex.com
a73 2 – 512K x 8 SRAMs & 2 – 512K x 8 Flash Die in
One MCM
a73 Access Times of 25ns (SRAM) and 60ns (Flash) or
35ns (SRAM) and 70 or 90ns (Flash)
a73 512K x 16 SRAM
a73 512K x 16 5V Flash
a73 Organized as 512K x 16 of SRAM and 512K x 16 of
Flash Memory with Separate Data Buses
a73 Both Blocks of Memory are User Configurable as
1M x 8
a73 Low Power CMOS
a73 Input and Output TTL Compatible Design
a73 MIL-PRF-38534 Compliant MCMs Available
a73 Decoupling Capacitors and Multiple Grounds for Low
Noise
a73 Industrial and Military Temperature Ranges
a73 Industry Standard Pinouts
a73 Packaging – Hermetic Ceramic
a71 66 Pin, 1.08" x 1.08" x .160" PGA Type, No Shoulder,
Aeroflex code# "P3"
a71 66 Pin, 1.08" x 1.08" x .185" PGA Type, With
Shoulder, Aeroflex code# "P7"
a71 68 Lead, .94" x .94" x .140" Single-Cavity Small
Outline Gull Wing, Aeroflex code# "F18" (Drops into
the 68 Lead JEDEC .99"SQ CQFJ footprint)
a73 DESC SMD Pending – 5962-96901
FLASH MEMORY FEATURES
a73 Sector Architecture (Each Die)
a71 8 Equal Sectors of 64K bytes each
a71 Any combination of sectors can be erased with one
command sequence.
a73 +5V Programing, 5V ±10% Supply
a73 Embedded Erase and Program Algorithms
a73 Hardware and Software Write Protection
a73 Internal Program Control Time.
a73 10,000 Erase / Program Cycles
Pin Description
FI/O0-15 Flash Data I/O
SI/O0-15 SRAM Data I/O
A0–18 Address Inputs
FWE1-2 Flash Write Enables
SWE1-2 SRAM Write Enables
FCE1-2 Flash Chip Enables
SCE1-2 SRAM Chip Enables
OE Output Enable
NC Not Connected
VCC Power Supply
GND Ground
512Kx8

FCE2
OE
A0 – A18
SI/O0-7 SI/O8-15 FI/O0-7 FI/O8-15
8 8 8 8
FCE1 FWE2FWE1SWE2SWE1 SCE1 SCE2
Block Diagram – PGA Type Packages (P3 & P7) & CQFP (F18)
SRAM
512Kx8
SRAM
512Kx8
Flash
512Kx8
Flash
512Kx16 SRAM/FLASH Multichip Module
ACT–SF512K16 High Speed
Note: Programming information available upon request