FEATURES
eroflex Circuit Technology - Advanced Multichip Modules © SCD3851 REV A 5/21/98
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CIRCUIT TECHNOLOGY
www.aeroflex.com
a73 4 – 128K x 8 SRAMs & 4 – 512K x 8 Flash Die in
One MCM
a73 Access Times of 25ns, 35ns (SRAM) and
60ns, 70ns, 90ns (Flash)
a73 Organized as 128K x 32 of SRAM and 512K x 32
of Flash Memory with Common Data Bus
a73 Low Power CMOS
a73 Input and Output TTL Compatible Design
a73 MIL-PRF-38534 Compliant MCMs Available
a73 Decoupling Capacitors and Multiple Grounds for
Low Noise
a73 Commercial, Industrial and Military Temperature
Ranges
a73 Industry Standard Pinouts
a73 TTL Compatible Inputs and Outputs
a73 Packaging – Hermetic Ceramic
a71 66–Lead, PGA-Type, 1.385"SQ x 0.245"max,
Aeroflex code# "P1,P5 with/without shoulders)"
a71 68–Lead, Dual-Cavity CQFP(F2), 0.88"SQ x
.20"max (.18 max thickness available, contact
factory for details) (Drops into the 68 Lead
JEDEC .99"SQ CQFJ footprint)
FLASH MEMORY FEATURES
a73 Sector Architecture (Each Die)
a71 8 Equal Sectors of 64K bytes each
a71 Any combination of sectors can be erased with
one command sequence.
a73 +5V Programing, +5V Supply
a73 Embedded Erase and Program Algorithms
a73 Hardware and Software Write Protection
a73 Page Program Operation and Internal Program
Control Time.
a73 10,000 Erase/Program Cycles
Block Diagram – PGA Type Package(P1 & P5) & CQFP(F2)
ACT-SF41632 High Speed
Multichip Module
128Kx32 SRAM / 512Kx32 Flash
OE
FWE1
SCE
I/O8-15 I/O16-23I/O0-7 I/O24-31
512K X 8 FLASH
A0–A18
128K X 8 SRAM
512K X 8 FLASH
128K X 8 SRAM
512K X 8 FLASH
128K X 8 SRAM
512K X 8 FLASH
128K X 8 SRAM
FCE
SWE1 FWE2 SWE2 FWE3 SWE3 FWE4 SWE4 PIN DESCRIPTION
I/O0-31 Data I/O
A0–18 Address Inputs
FWE1-4 Flash Write Enables
SWE1-4 SRAM Write Enables
FCE Flash Chip Enable
SCE SRAM Chip Enable
OE Output Enable
NC Not Connected
VCC Power Supply
GND Ground