1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
ACS10MS
Radiation Hardened
Triple Three-Input NAND Gate
Pinouts
14 LEAD CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR CDIP2-T14, LEAD FINISH C
TOP VIEW
14 LEAD CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR CDFP3-F14, LEAD FINISH C
TOP VIEW
A1
B1
A2
B2
C2
Y2
GND
VCC
C1
Y1
C3
B3
A3
Y3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
14
13
12
11
10
9
8
2
3
4
5
6
7
1A1
B1
A2
B2
C2
Y2
GND
VCC
C1
Y1
C3
B3
A3
Y3
Features
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose 300K RAD (Si)
• Single Event Upset (SEU) Immunity
<1 x 10
-10
Errors/Bit-Day (Typ)
• SEU LET Threshold >80 MEV-cm
2
/mg
• Dose Rate Upset >10
11
RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55
o
C to +125
o
C
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current ≤1µA at VOL, VOH
Description
The Intersil ACS10MS is a radiation hardened triple three-input
NAND gate. A high on all inputs forces the output to a low state.
The ACS10MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of the
radiation hardened, high-speed, CMOS/SOS Logic Family.
April 1995
Truth Table
INPUTS OUTPUT
An Bn Cn Yn
LLL H
LLH
LHL H
LHH
HLL H
HLH
HHL H
HHH L
NOTE: L = Logic Level Low, H = Logic Level High
Functional Diagram
An
Bn Yn
(6, 8, 12)
(1, 3, 9)
(2, 4, 10)
(5, 11, 13)
Cn
Ordering Information
PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE
ACS10DMSR -55
o
C to +125
o
C Intersil Class S Equivalent 14 Lead SBDIP
ACS10KMSR -55
o
C to +125
o
C Intersil Class S Equivalent 14 Lead Ceramic Flatpack
ACS10D/Sample +25
o
C Sample 14 Lead SBDIP
ACS10K/Sample +25
o
C Sample 14 Lead Ceramic Flatpack
ACS10HMSR +25
o
C Die Die
Spec Number 518814
File Number 3630