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November 1995COPYRIGHT ' INTEL CORPORATION, 1995 Order Number: 290501-003
A28F400BX-T/B
4-MBIT (256K x16, 512K x8) BOOT BLOCK FLASH
MEMORY FAMILY
Automotive
Y
x8/x16 Input/Output Architecture
— A28F400BX-T, A28F400BX-B
— For High Performance and High
Integration 16-bit and 32-bit CPUs
Y
Optimized High Density Blocked
Architecture
— One 16 KB Protected Boot Block
— Two 8 KB Parameter Blocks
— One 96 KB Main Block
— Three 128 KB Main Blocks
— Top or Bottom Boot Locations
Y
Extended Cycling Capability
— 1,000 Block Erase Cycles
Y
Automated Word/Byte Write and Block
Erase
— Command User Interface
— Status Register
— Erase Suspend Capability
Y
SRAM-Compatible Write Interface
Y
Automatic Power Savings Feature
— 1 mA Typical I
CC
Active Current in
Static Operation
Y
Very High-Performance Read
— 90 ns Maximum Access Time
— 45 ns Maximum Output Enable Time
Y
Low Power Consumption
— 25 mA Typical Active Read Current
Y
Deep Power-Down/Reset Input
— Acts as Reset for Boot Operations
Y
Automotive Temperature Operation
—
b
40§Cto
a
125§C
Y
Write Protection for Boot Block
Y
Hardware Data Protection Feature
— Erase/Write Lockout During Power
Transitions
Y
Industry Standard Surface Mount
Packaging
— JEDEC ROM Compatible
44-Lead PSOP
Y
12V Word/Byte Write and Block Erase
—V
PP
e
12V g5% Standard
Y
ETOX
TM
III Flash Technology
— 5V Read