74VHCT541A
器件描述：Octal Buffer/Line Driver with 3-STATE Outputs
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：83.28KB，共7页
Sponsor by e络盟器件资料摘要：
© 2005 Fairchild Semiconductor Corporation DS500013 www.fairchildsemi.com
June 1997
Revised April 2005
7
4
VH
CT5
41A
Oct
a
l
Buf
f
er
/Li
ne D
r
ive
r
w
i
th 3-
S
T
A
T
E O
u
t
put
s
74VHCT541A
Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The VHCT541A is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It achieves
the high-speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi-
pation.
The VHCT541A is an octal buffer/line driver designed to be
employed as memory and address drivers, clock drivers
and bus oriented transmitter/receivers.
This device is similar in function to the VHCT244A while
providing flow-through architecture (inputs on opposite side
from outputs). This pinout arrangement makes this device
especially useful as an output port for microprocessors,
allowing ease of layout and greater PC board density.
Protection circuits ensure that 0V to 7V can be applied to
the input and output (Note 1) pins without regard to the
supply voltage. This device can be used to interface 3V to
5V systems and two supply systems such as battery
backup. This circuit prevents device destruction due to mis-
matched supply and input voltages.
Note 1: Outputs in OFF-state.
Features
a73 High Speed: t
PD
c32 5.5 ns (typ) at V
CC
c32 5V
a73 Low power dissipation: I
CC
c32 4 c80A (max) at T
A
c32 25c113C
a73 Power down protection is provided on all inputs and
outputs
a73 Pin and function compatible with 74HCT541
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
IEEE/IEC
Pin Descriptions
Connection Diagram
Truth Table
H c32 HIGH Voltage Level L c32 LOW Voltage Level
X c32 Immaterial Z c32 High Impedance
Order Number Package Number Package Description
74VHCT541AM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74VHCT541ASJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHCT541AMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHCT541AN N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Pin Names Description
OE
1
, OE
2
3-STATE Output Enable Inputs
I
0
- I
7
Inputs
O
0
- O
7
3-STATE Outputs
Inputs Outputs
OE
1
OE
2
I
LLHH
HXX Z
XHX Z
LLL L
June 1997
Revised April 2005
7
4
VH
CT5
41A
Oct
a
l
Buf
f
er
/Li
ne D
r
ive
r
w
i
th 3-
S
T
A
T
E O
u
t
put
s
74VHCT541A
Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The VHCT541A is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It achieves
the high-speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi-
pation.
The VHCT541A is an octal buffer/line driver designed to be
employed as memory and address drivers, clock drivers
and bus oriented transmitter/receivers.
This device is similar in function to the VHCT244A while
providing flow-through architecture (inputs on opposite side
from outputs). This pinout arrangement makes this device
especially useful as an output port for microprocessors,
allowing ease of layout and greater PC board density.
Protection circuits ensure that 0V to 7V can be applied to
the input and output (Note 1) pins without regard to the
supply voltage. This device can be used to interface 3V to
5V systems and two supply systems such as battery
backup. This circuit prevents device destruction due to mis-
matched supply and input voltages.
Note 1: Outputs in OFF-state.
Features
a73 High Speed: t
PD
c32 5.5 ns (typ) at V
CC
c32 5V
a73 Low power dissipation: I
CC
c32 4 c80A (max) at T
A
c32 25c113C
a73 Power down protection is provided on all inputs and
outputs
a73 Pin and function compatible with 74HCT541
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
IEEE/IEC
Pin Descriptions
Connection Diagram
Truth Table
H c32 HIGH Voltage Level L c32 LOW Voltage Level
X c32 Immaterial Z c32 High Impedance
Order Number Package Number Package Description
74VHCT541AM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74VHCT541ASJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHCT541AMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHCT541AN N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Pin Names Description
OE
1
, OE
2
3-STATE Output Enable Inputs
I
0
- I
7
Inputs
O
0
- O
7
3-STATE Outputs
Inputs Outputs
OE
1
OE
2
I
LLHH
HXX Z
XHX Z
LLL L