October 1987
Revised January 1999
MM74C86
Q
u
ad 2-
Inp
u
t
EXC
LUSI
VE-OR Gat
e
© 1999 Fairchild Semiconductor Corporation DS005887.prf www.fairchildsemi.com
MM74C86
Quad 2-Input EXCLUSIVE-OR Gate
General Description
The MM74C86 employs complementary MOS (CMOS)
transistors to achieve wide power supply operating range,
low power consumption and high noise margin these gates
provide basic functions used in the implementation of digi-
tal integrated circuit systems. The N- and P-channel
enhancement mode transistors provide a symmetrical cir-
cuit with output swing essentially equal to the supply volt-
age. No DC power other than that caused by leakage
current is consumed during static condition. All inputs are
protected from damage due to static discharge by diode
clamps to V
CC
and GND.
Features
a73 Wide supply voltage range: 3.0V to 15V
a73 Guaranteed noise margin: 1.0V
a73 High noise immunity: 0.45 V
CC
(typ.)
a73 Low power: TTL compatibility:
Fan out of 2 driving 74L
a73 Low power consumption: 10 nW/package (typ.)
a73 The MM74C86 follows the MM74LS86 Pinout

Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP and SOIC
Top View
Truth Table
H = HIGH Level
L = LOW Level
Order Number Package Number Package Description
MM74C86M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74C86N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Inputs Output
ABY
LLL
LHH
HL
HHL