March 1993
Revised April 1999
7
4
VH
C57
4

Oct
a
l D-T
ype Fli
p
-
F
lop wit
h

3-
ST
A
T
E Output
s
© 1999 Fairchild Semiconductor Corporation DS011565.prf www.fairchildsemi.com
74VHC574
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The VHC574 is an advanced high speed CMOS octal flip-
flop with 3-STATE output fabricated with silicon gate CMOS
technology. It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation. This 8-bit D-type flip-flop is
controlled by a clock input (CP) and an output enable input
(OE). When the OE input is HIGH, the eight outputs are in
a high impedance state.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery back up. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
a73 High Speed: t
PD
= 5.6 ns (typ) at V
CC
= 5V
a73 High Noise Immunity: V
NIH
= V
NIL
= 28% V
CC
(Min)
a73 Power Down Protection is provided on all inputs
a73 Low Noise: V
OLP
= 0.6V (typ)
a73 Low Power Dissipation: I
CC
= 4 µA (Max) @ T
A
= 25°C
a73 Pin and Function Compatible with 74HC574

Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Order Number Package Number Package Description
74VHC574M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74VHC574SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC574MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153
74VHC574N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
D
0
–D
7
Data Inputs
CP Clock Pulse Input
OE 3-STATE Output Enable Input
O
0
–O
7
3-STATE Outputs