74VHC573
器件描述：Octal D-Type Latch with 3-STATE Outputs
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：104.64KB，共8页
Sponsor by e络盟器件资料摘要：
© 2005 Fairchild Semiconductor Corporation DS011563 www.fairchildsemi.com
March 1993
Revised May 2005
7
4
VH
C57
3
Oct
a
l
D-
T
ype Lat
ch
w
i
t
h
3-
ST
A
T
E
O
u
tput
s
74VHC573
Octal D-Type Latch with 3-STATE Outputs
General Description
The VHC573 is an advanced high speed CMOS octal latch
with 3-STATE output fabricated with silicon gate CMOS
technology. It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation. This 8-bit D-type latch is con-
trolled by a latch enable input (LE) and an Output Enable
input (OE). When the OE input is HIGH, the eight outputs
are in a high impedance state.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery back up. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
a73 High Speed: t
PD
c32 5.0 ns (typ) at V
CC
c32 5V
a73 High Noise Immunity: V
NIH
c32 V
NIL
c32 28% V
CC
(Min)
a73 Power Down Protection is provided on all inputs
a73 Low Noise: V
OLP
c32 0.6V (typ)
a73 Low Power Dissipation: I
CC
c32 4 c80A (Max) @ T
A
c32 25c113C
a73 Pin and function compatible with 74HC573
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Order Number Package Number Package Description
74VHC573M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74VHC573SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC573N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Pin Names Description
D
0
–D
7
Data Inputs
LE Latch Enable Input
OE 3-STATE Output Enable Input
O
0
–O
7
3-STATE Outputs
March 1993
Revised May 2005
7
4
VH
C57
3
Oct
a
l
D-
T
ype Lat
ch
w
i
t
h
3-
ST
A
T
E
O
u
tput
s
74VHC573
Octal D-Type Latch with 3-STATE Outputs
General Description
The VHC573 is an advanced high speed CMOS octal latch
with 3-STATE output fabricated with silicon gate CMOS
technology. It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation. This 8-bit D-type latch is con-
trolled by a latch enable input (LE) and an Output Enable
input (OE). When the OE input is HIGH, the eight outputs
are in a high impedance state.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery back up. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
a73 High Speed: t
PD
c32 5.0 ns (typ) at V
CC
c32 5V
a73 High Noise Immunity: V
NIH
c32 V
NIL
c32 28% V
CC
(Min)
a73 Power Down Protection is provided on all inputs
a73 Low Noise: V
OLP
c32 0.6V (typ)
a73 Low Power Dissipation: I
CC
c32 4 c80A (Max) @ T
A
c32 25c113C
a73 Pin and function compatible with 74HC573
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Order Number Package Number Package Description
74VHC573M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74VHC573SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC573N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Pin Names Description
D
0
–D
7
Data Inputs
LE Latch Enable Input
OE 3-STATE Output Enable Input
O
0
–O
7
3-STATE Outputs