74ACT377
器件描述：Octal D-Type Flip-Flop with Clock Enable
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：113.73KB，共9页
Sponsor by e络盟器件资料摘要：
© 2005 Fairchild Semiconductor Corporation DS009961 www.fairchildsemi.com
November 1988
Revised March 2005
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74AC377 74ACT377
Octal D-Type Flip-Flop with Clock Enable
General Description
The AC/ACT377 has eight edge-triggered, D-type flip-flops
with individual D inputs and Q outputs. The common buff-
ered Clock (CP) input loads all flip-flops simultaneously,
when the Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
The CE input must be stable only one setup time prior to
the LOW-to-HIGH clock transition for predictable operation.
Features
a73 I
CC
reduced by 50%
a73 Ideal for addressable register applications
a73 Clock enable for address and data synchronization
applications
a73 Eight edge-triggered D-type flip-flops
a73 Buffered common clock
a73 Outputs source/sink 24 mA
a73 See 273 for master reset version
a73 See 373 for transparent latch version
a73 See 374 for 3-STATE version
a73 ACT377 has TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Connection Diagram Pin Descriptions
FACTc165 is a trademark of Fairchild Semiconductor Corporation.
Order Number
Package
Package Description
Number
74AC377SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74AC377SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC377MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC377MTCX_NL
(Note 1)
MTC20 Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74AC377PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74ACT377SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ACT377SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT377MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT377PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Pin Names Description
D
0
–D
7
Data Inputs
CE Clock Enable (Active LOW)
Q
0
–Q
7
Data Outputs
CP Clock Pulse Input
November 1988
Revised March 2005
7
4
AC
3
77
• 74ACT377 O
c
t
a
l D-T
ype Fli
p
-
F
lop wit
h
Cl
ock
Ena
b
le
74AC377 74ACT377
Octal D-Type Flip-Flop with Clock Enable
General Description
The AC/ACT377 has eight edge-triggered, D-type flip-flops
with individual D inputs and Q outputs. The common buff-
ered Clock (CP) input loads all flip-flops simultaneously,
when the Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
The CE input must be stable only one setup time prior to
the LOW-to-HIGH clock transition for predictable operation.
Features
a73 I
CC
reduced by 50%
a73 Ideal for addressable register applications
a73 Clock enable for address and data synchronization
applications
a73 Eight edge-triggered D-type flip-flops
a73 Buffered common clock
a73 Outputs source/sink 24 mA
a73 See 273 for master reset version
a73 See 373 for transparent latch version
a73 See 374 for 3-STATE version
a73 ACT377 has TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Connection Diagram Pin Descriptions
FACTc165 is a trademark of Fairchild Semiconductor Corporation.
Order Number
Package
Package Description
Number
74AC377SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74AC377SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC377MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC377MTCX_NL
(Note 1)
MTC20 Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74AC377PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74ACT377SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ACT377SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT377MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT377PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Pin Names Description
D
0
–D
7
Data Inputs
CE Clock Enable (Active LOW)
Q
0
–Q
7
Data Outputs
CP Clock Pulse Input