74VHC273
器件描述：Octal D-Type Flip-Flop
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：91.77KB，共7页
Sponsor by e络盟器件资料摘要：
April 1994
Revised April 1999
7
4
VH
C27
3
Oct
a
l D-T
ype Fli
p
-
F
lop
© 1999 Fairchild Semiconductor Corporation DS011670.prf www.fairchildsemi.com
74VHC273
Octal D-Type Flip-Flop
General Description
The VHC273 is an advanced high speed CMOS Octal D-
type flip-flop fabricated with silicon gate CMOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation.
The register has a common buffered Clock (CP) which is
fully edge-triggered. The state of each D input, one setup
time before the LOW-to-HIGH clock transition, is trans-
ferred to the corresponding flip-flop’s Q output. The Master
Reset (MR) input will clear all flip-flops simultaneously. All
outputs will be forced LOW independently of Clock or Data
inputs by a LOW voltage level on the MR input.
An input protection circuit insures that 0V to 7V can be
applied to the inputs pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
a73 High Speed: f
MAX
= 165 MHz (typ) at V
CC
= 5V
a73 Low power dissipation: I
CC
= 4 µA (max) at T
A
= 25°C
a73 High noise immunity: V
NIH
= V
NIL
= 28% V
CC
(min)
a73 Power down protection is provided on all inputs
a73 Low noise: V
OLP
= 0.9V (max)
a73 Pin and function compatible with 74HC273
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
Order Number Package Number Package Description
74VHC273M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74VHC273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC273MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC273N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
D
0
–D
7
Data Inputs
MR
Master Reset
CP Clock Pulse Input
Q
0
–Q
7
Data Outputs
Revised April 1999
7
4
VH
C27
3
Oct
a
l D-T
ype Fli
p
-
F
lop
© 1999 Fairchild Semiconductor Corporation DS011670.prf www.fairchildsemi.com
74VHC273
Octal D-Type Flip-Flop
General Description
The VHC273 is an advanced high speed CMOS Octal D-
type flip-flop fabricated with silicon gate CMOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation.
The register has a common buffered Clock (CP) which is
fully edge-triggered. The state of each D input, one setup
time before the LOW-to-HIGH clock transition, is trans-
ferred to the corresponding flip-flop’s Q output. The Master
Reset (MR) input will clear all flip-flops simultaneously. All
outputs will be forced LOW independently of Clock or Data
inputs by a LOW voltage level on the MR input.
An input protection circuit insures that 0V to 7V can be
applied to the inputs pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
a73 High Speed: f
MAX
= 165 MHz (typ) at V
CC
= 5V
a73 Low power dissipation: I
CC
= 4 µA (max) at T
A
= 25°C
a73 High noise immunity: V
NIH
= V
NIL
= 28% V
CC
(min)
a73 Power down protection is provided on all inputs
a73 Low noise: V
OLP
= 0.9V (max)
a73 Pin and function compatible with 74HC273
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
Order Number Package Number Package Description
74VHC273M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74VHC273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC273MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC273N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
D
0
–D
7
Data Inputs
MR
Master Reset
CP Clock Pulse Input
Q
0
–Q
7
Data Outputs