74VHC245
OCTAL BUS
TRANSCEIVER (3-STATE)
PRELIMINARY DATA
June 1999
ORDER CODES :
74VHC245M 74VHC245T
M
(Micro Package)
n HIGH SPEED: tPD = 4.0 ns (TYP.) at VCC =5V
n LOW POWER DISSIPATION:
ICC =4 µA (MAX.) at TA =25
o
C
n HIGH NOISE IMMUNITY:
VNIH =VNIL =28%VCC (MIN.)
n POWERDOWN PROTECTIONON CONTROL
INPUTS
n SYMMETRICAL OUTPUT IMPEDANCE:
|IOH|=IOL = 8 mA (MIN)
n BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
n OPERATING VOLTAGE RANGE:
VCC (OPR)= 2V to 5.5V
n PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 245
n IMPROVED LATCH-UP IMMUNITY
n LOW NOISEV
OLP
= 0.9V(Max.)
DESCRIPTION
The 74VHC245 is an advanced high-speed
CMOS OCTAL BUS TRANSCEIVER (3-STATE)
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology.
This IC is intended for two-way asynchronous
communication between data busses; the
direction of data trasmission is determined by the
level of the DIR input. The enable input G can be
T
(TSSOP Package)
used to disable the device so that the busses are
effectively isolated.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2kV ESD immunity and transient excess
voltage.
IT IS PROHIBITED TO APPLY A SIGNAL TO A
TERMINAL WHEN IT IS IN OUTPUT MODE
AND WHEN A BUS TERMINAL IS FLOATING
(HIGH IMPEDANCE STATE) IT IS REQUESTED
TO FIX THE INPUT LEVEL BY MEANS OF
EXTERNAL PULL DOWN OR PULL UP
RESISTOR.
PIN CONNECTION AND IEC LOGIC SYMBOLS
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