74VHC175
器件资料摘要：
August 1993
Revised April 1999
7
4
VH
C17
5
Quad D-T
ype Fli
p
-F
lop
© 1999 Fairchild Semiconductor Corporation DS011637.prf www.fairchildsemi.com
74VHC175
Quad D-Type Flip-Flop
General Description
The VHC175 is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It achieves
the high-speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi-
pation.
The VHC175 is a high-speed quad D-type flip-flop. The
device is useful for general flip-flop requirements where
clock and clear inputs are common. The information on the
D inputs is stored during the LOW-to-HIGH clock transition.
Both true and complemented outputs of each flip-flop are
provided. A Master Reset input resets all flip-flops, inde-
pendent of the Clock or D inputs, when LOW.
An input protection circuit insures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
a73 High Speed: f
MAX
= 210 MHz (typ) at V
CC
= 5V
a73 Low power dissipation: I
CC
= 4 µA (max) at T
A
= 25°C
a73 High noise immunity: V
NIH
= V
NIL
= 28% V
CC
(min)
a73 Power down protection is provided on all inputs
a73 Low noise: V
OLP
= 0.8V (max)
a73 Pin and function compatible with 74HC175
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Pin Descriptions
Logic Symbols
IEEE/IEC
Order Number Package Number Package Description
74VHC175M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74VHC175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC175MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC175N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
D
0
–D
3
Data Inputs
CP Clock Pulse Input
MR Master Reset Input
Q
0
–Q
3
True Outputs
Q
0
–Q
3
Complement Outputs
Revised April 1999
7
4
VH
C17
5
Quad D-T
ype Fli
p
-F
lop
© 1999 Fairchild Semiconductor Corporation DS011637.prf www.fairchildsemi.com
74VHC175
Quad D-Type Flip-Flop
General Description
The VHC175 is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It achieves
the high-speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi-
pation.
The VHC175 is a high-speed quad D-type flip-flop. The
device is useful for general flip-flop requirements where
clock and clear inputs are common. The information on the
D inputs is stored during the LOW-to-HIGH clock transition.
Both true and complemented outputs of each flip-flop are
provided. A Master Reset input resets all flip-flops, inde-
pendent of the Clock or D inputs, when LOW.
An input protection circuit insures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
a73 High Speed: f
MAX
= 210 MHz (typ) at V
CC
= 5V
a73 Low power dissipation: I
CC
= 4 µA (max) at T
A
= 25°C
a73 High noise immunity: V
NIH
= V
NIL
= 28% V
CC
(min)
a73 Power down protection is provided on all inputs
a73 Low noise: V
OLP
= 0.8V (max)
a73 Pin and function compatible with 74HC175
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Pin Descriptions
Logic Symbols
IEEE/IEC
Order Number Package Number Package Description
74VHC175M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74VHC175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC175MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC175N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
D
0
–D
3
Data Inputs
CP Clock Pulse Input
MR Master Reset Input
Q
0
–Q
3
True Outputs
Q
0
–Q
3
Complement Outputs