74VHC174
HEX D-TYPE FLIP FLOP WITH CLEAR
PRELIMINARY DATA
June 1999
n HIGH SPEED:
f
MAX
=175 MHz (TYP.) at V
CC
=5V
n LOW POWER DISSIPATION:
I
CC
=4 µA (MAX.) at T
A
=25
o
C
n HIGH NOISE IMMUNITY:
VNIH =VNIL =28%VCC (MIN.)
n POWERDOWN PROTECTIONON INPUTS
n SYMMETRICAL OUTPUT IMPEDANCE:
|IOH|=IOL = 8 mA (MIN)
n BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
n OPERATING VOLTAGE RANGE:
VCC (OPR)= 2V to 5.5V
n PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 174
n IMPROVED LATCH-UP IMMUNITY
n LOW NOISE: V
OLP
= 0.8V(Max.)
DESCRIPTION
The 74VHC174 is an advanced high-speed
CMOS HEX D-TYPE FLIP FLOP WITH CLEAR
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology.
Information signals applied to D inputs are
transfered to the Q outputs on the positive going
edge of the clock pulse.
When the CLEAR input is held low, the Q outputs
are held low independentlyof the other inputs.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74VHC174M 74VHC174T

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