74VHC138
器件描述：3-to-8 Decoder/Demultiplexer
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：65.66KB，共7页
Sponsor by e络盟器件资料摘要：
November 1992
Revised April 1999
7
4
VH
C13
8
3-
to-
8
D
e
c
oder/
D
em
ul
ti
pl
exer
© 1999 Fairchild Semiconductor Corporation DS011537.prf www.fairchildsemi.com
74VHC138
3-to-8 Decoder/Demultiplexer
General Description
The VHC138 is an advanced high speed CMOS 3-to-8
decoder/demultiplexer fabricated with silicon gate CMOS
technology. It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
When the device is enabled, 3 binary select inputs (A
0
, A
1
and A
2
) determine which one of the outputs (O
0
–O
7
) will go
LOW. When enable input E
3
is held LOW or either E
1
or E
2
is held HIGH, decoding function is inhibited and all outputs
go HIGH. E
3
, E
1
and E
2
inputs are provided to ease cas-
cade connection and for use as an address decoder for
memory systems. An input protection circuit ensures that
0V to 7V can be applied to the input pins without regard to
the supply voltage. This device can be used to interface 5V
to 3V systems and two supply systems such as battery
back up. This circuit prevents device destruction due to
mismatched supply and input voltages.
Features
a73 High Speed: t
PD
= 5.7ns (typ) at T
A
= 25°C
a73 Low power dissipation: I
CC
= 4 µA (max.) at T
A
= 25°C
a73 High noise immunity: V
NIH
= V
NIL
= 28% V
CC
(min.)
a73 Power down protection provided on all inputs
a73 Pin and function compatible with 74HC138
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
Order Number Package Number Package Description
74VHC138M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
74VHC138SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC138MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC138N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
A
0
–A
2
Address Inputs
E
1
–E
2
Enable Inputs
E
3
Enable Input
O
0
–O
7
Outputs
Revised April 1999
7
4
VH
C13
8
3-
to-
8
D
e
c
oder/
D
em
ul
ti
pl
exer
© 1999 Fairchild Semiconductor Corporation DS011537.prf www.fairchildsemi.com
74VHC138
3-to-8 Decoder/Demultiplexer
General Description
The VHC138 is an advanced high speed CMOS 3-to-8
decoder/demultiplexer fabricated with silicon gate CMOS
technology. It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
When the device is enabled, 3 binary select inputs (A
0
, A
1
and A
2
) determine which one of the outputs (O
0
–O
7
) will go
LOW. When enable input E
3
is held LOW or either E
1
or E
2
is held HIGH, decoding function is inhibited and all outputs
go HIGH. E
3
, E
1
and E
2
inputs are provided to ease cas-
cade connection and for use as an address decoder for
memory systems. An input protection circuit ensures that
0V to 7V can be applied to the input pins without regard to
the supply voltage. This device can be used to interface 5V
to 3V systems and two supply systems such as battery
back up. This circuit prevents device destruction due to
mismatched supply and input voltages.
Features
a73 High Speed: t
PD
= 5.7ns (typ) at T
A
= 25°C
a73 Low power dissipation: I
CC
= 4 µA (max.) at T
A
= 25°C
a73 High noise immunity: V
NIH
= V
NIL
= 28% V
CC
(min.)
a73 Power down protection provided on all inputs
a73 Pin and function compatible with 74HC138
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
Order Number Package Number Package Description
74VHC138M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
74VHC138SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC138MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC138N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
A
0
–A
2
Address Inputs
E
1
–E
2
Enable Inputs
E
3
Enable Input
O
0
–O
7
Outputs