74VCXR162601
器件描述：Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and 26ヘ Series Resistors in the Outputs
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：60.51KB，共7页
Sponsor by e络盟器件资料摘要：
August 1998
Revised April 1999
7
4
VC
XR162
601
Lo
w
V
o
lt
age
1
8
-Bi
t
Univer
sal Bus T
r
ansce
iver
s
wi
th 3.6V T
o
ler
ant
I
nputs and O
u
tput
s
and
26
Ω
Ser
i
es
Resi
stor
s i
n
the
Output
s
© 1999 Fairchild Semiconductor Corporation DS500171.prf www.fairchildsemi.com
74VCXR162601
Low Voltage 18-Bit Universal Bus Transceivers with 3.6V
Tolerant Inputs and Outputs and 26Ω Series Resistors in
the Outputs
General Description
The VCXR162601, 18-bit universal bus transceiver, com-
bines D-type latches and D-type flip-flops to allow data flow
in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. The clock can be con-
trolled by the clock-enable (CLKENAB and CLKENBA)
inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is HIGH. When LEAB is
LOW, the A data is latched if CLKAB is held at a HIGH-to-
LOW logic level. If LEAB is LOW, the A bus data is stored
in the latch/flip-flop on the LOW-to-HIGH transition of
CLKAB. Output-enable OEAB is active-LOW. When OEAB
is HIGH, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, CLKBA and CLKENBA.
The 74VCXR162601 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The VCXR162601 is also designed with 26Ω series resis-
tors on both the A and B Port outputs. This design reduces
line noise in applications such as memory address drivers,
clock drivers, and bus transceivers/transmitters.
Features
a73 1.65–3.6V V
CC
supply operation
a73 3.6V tolerant inputs and outputs
a73 26Ω series resistors on both the A and B Port outputs.
a73 t
PD
(A to B, B to A)
3.8 ns max for 3.0V to 3.6V V
CC
4.6 ns max for 2.3V to 2.7V V
CC
9.2 ns max for 1.65V to 1.95V V
CC
a73 Power-down HIGH impedance inputs and outputs
a73 Supports live insertion/withdrawal (Note 1)
a73 Static Drive (I
OH
/I
OL
)
±12 mA @ 3.0V V
CC
±8 mA @ 2.3V V
CC
±3 mA @ 1.65V V
CC
a73 Uses patented noise/EMI reduction circuitry
a73 Latchup performance exceeds 300 mA
a73 ESD performance:
Human body model > 2000V
Machine model >200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number Package Number Package Description
74VCXR162601MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Revised April 1999
7
4
VC
XR162
601
Lo
w
V
o
lt
age
1
8
-Bi
t
Univer
sal Bus T
r
ansce
iver
s
wi
th 3.6V T
o
ler
ant
I
nputs and O
u
tput
s
and
26
Ω
Ser
i
es
Resi
stor
s i
n
the
Output
s
© 1999 Fairchild Semiconductor Corporation DS500171.prf www.fairchildsemi.com
74VCXR162601
Low Voltage 18-Bit Universal Bus Transceivers with 3.6V
Tolerant Inputs and Outputs and 26Ω Series Resistors in
the Outputs
General Description
The VCXR162601, 18-bit universal bus transceiver, com-
bines D-type latches and D-type flip-flops to allow data flow
in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. The clock can be con-
trolled by the clock-enable (CLKENAB and CLKENBA)
inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is HIGH. When LEAB is
LOW, the A data is latched if CLKAB is held at a HIGH-to-
LOW logic level. If LEAB is LOW, the A bus data is stored
in the latch/flip-flop on the LOW-to-HIGH transition of
CLKAB. Output-enable OEAB is active-LOW. When OEAB
is HIGH, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, CLKBA and CLKENBA.
The 74VCXR162601 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The VCXR162601 is also designed with 26Ω series resis-
tors on both the A and B Port outputs. This design reduces
line noise in applications such as memory address drivers,
clock drivers, and bus transceivers/transmitters.
Features
a73 1.65–3.6V V
CC
supply operation
a73 3.6V tolerant inputs and outputs
a73 26Ω series resistors on both the A and B Port outputs.
a73 t
PD
(A to B, B to A)
3.8 ns max for 3.0V to 3.6V V
CC
4.6 ns max for 2.3V to 2.7V V
CC
9.2 ns max for 1.65V to 1.95V V
CC
a73 Power-down HIGH impedance inputs and outputs
a73 Supports live insertion/withdrawal (Note 1)
a73 Static Drive (I
OH
/I
OL
)
±12 mA @ 3.0V V
CC
±8 mA @ 2.3V V
CC
±3 mA @ 1.65V V
CC
a73 Uses patented noise/EMI reduction circuitry
a73 Latchup performance exceeds 300 mA
a73 ESD performance:
Human body model > 2000V
Machine model >200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number Package Number Package Description
74VCXR162601MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide