1/12February 2003
a73 3.6V TOLERANT INPUTS AND OUTPUTS
a73 HIGH SPEED :
t
PD
= 3.0 ns (MAX.) at V
CC
=3.0to3.6V
t
PD
= 3.9 ns (MAX.) at V
CC
=2.3to2.7V
a73 POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
a73 SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
|=I
OL
= 24mA (MIN) at V
CC
=3.0V
|I
OH
|=I
OL
= 18mA (MIN) at V
CC
=2.3V
a73 OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2.3V to 3.6V
a73 PIN AND FUNCTION COMPATIBLE WITH
74 SERIES H16374
a73 BUS HOLD PROVIDED ON DATA INPUTS
a73 LATCH-UP PERFORMANCE EXCEEDS
300mA (JESD 17)
a73 ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74VCXH16374 is a low voltage CMOS 16 BIT
D-TYPE FLIP-FLOP with 3 STATE OUTPUTS
NON INVERTING fabricated with sub-micron
silicon gate and five-layer metal wiring C
2
MOS
technology. It is ideal for low power and very high
speed 2.3 to 3.6V applications; it can be interfaced
to 3.6V signal environment for both inputs and
outputs.
These 16 bit D-TYPE flip-flops are controlled by
two clock inputs (nCK) and two output enable
inputs (nOE).
Onthepositivetransitionofthe(nCK),thenQ
outputs will be set to the logic state that were
setup at the nD inputs.
While the (nOE) input is low, the 8 outputs (nQ)
will be in a normal state (HIGH or LOW logic level)
and while high level the outputs will be in a high
impedance state.
Any output control does not affect the internal
operation of flip flops; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
Bus hold on data inputs is provided in order to
eliminate the need for external pull-up or
pull-down resistor.
74VCXH16374
LOW VOLTAGE CMOS 16-BIT D-TYPE FLIP-FLOP (3-STATE)
WITH 3.6V TOLERANT INPUTS AND OUTPUTS
ORDER CODES
PACKAGE TUBE T & R
TSSOP 74VCXH16374TTR
TSSOP
PIN CONNECTION