© 2002 Fairchild Semiconductor Corporation DS500416 www.fairchildsemi.com
September 2000
Revised November 2002
7
4
VC
X32
244
Lo
w
V
o
lt
age
3
2
-Bi
t
Buff
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L
ine Dri
ver wit
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3.
6V T
o
l
e
ra
nt Input
s and
Out
puts
74VCX32244
Low Voltage 32-Bit Buffer/Line Driver
with 3.6V Tolerant Inputs and Outputs
General Description
The VCX32244 contains thirty-two non-inverting buffers
with 3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for 8-bit, 16-bit or full 32-bit operation.
The 74VCX32244 is designed for low voltage (1.2V to
3.6V) V
CC
applications with I/O capability up to 3.6V.
The 74VCX32244 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
a73 1.2V to 3.6V V
CC
supply operation
a73 3.6V tolerant inputs and outputs
a73 t
PD
2.5 ns max for 3.0V to 3.6V V
CC
a73 Power-off high impedance inputs and outputs
a73 Supports live insertion and withdrawal (Note 1)
a73 Static Drive (I
OH
/I
OL
)
±24 mA @ 3.0V V
CC
a73 Uses patented noise/EMI reduction circuitry
a73 Latch-up performance exceeds 300 mA
a73 ESD performance:
Human body model > 2000V
Machine model > 200V
a73 Packages in plastic Fine-Pitch Ball Grid Array (FBGA)
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.

Ordering Code:
Note 2: Ordering code “G” indicates Trays.
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Order Number Package Number Package Description
74VCX32244G
(Note 2)(Note 3)
BGA96A 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide