74VCX16373MTD
器件描述：Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：125.54KB，共10页
Sponsor by e络盟器件资料摘要：
© 2005 Fairchild Semiconductor Corporation DS500065 www.fairchildsemi.com
October 1997
Revised June 2005
7
4
VC
X16
373 Lo
w
V
o
lt
age
16-
Bit
T
r
ansp
arent
Lat
ch
w
i
th
3.
6V T
o
l
e
rant
I
nput
s
and
O
u
t
put
s
74VCX16373
Low Voltage 16-Bit Transparent Latch
with 3.6V Tolerant Inputs and Outputs
General Description
The VCX16373 contains sixteen non-inverting latches with
3-STATE outputs and is intended for bus oriented applica-
tions. The device is byte controlled. The flip-flops appear to
be transparent to the data when the Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup time
is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
a high impedance state.
The 74VCX16373 is designed for low voltage (1.2V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The 74VCX16373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
a73 1.2V to 3.6V V
CC
supply operation
a73 3.6V tolerant inputs and outputs
a73 t
PD
(I
n
to O
n
)
3.0 ns max for 3.0V to 3.6V V
CC
a73 Power-off high impedance inputs and outputs
a73 Support live insertion and withdrawal (Note 1)
a73 Static Drive (I
OH
/I
OL
)
c11424 mA @ 3.0V V
CC
a73 Uses patented noise/EMI reduction circuitry
a73 Latch-up performance exceeds 300 mA
a73 ESD performance:
Human body model c33 2000V
Machine model c33 200V
a73 Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Note 2: Ordering Code “G” indicates Trays.
Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Order Number Package Number Package Description
74VCX16373G
(Note 2)(Note 3)
BGA54A
(Preliminary)
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74VCX16373MTD
(Note 3)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
October 1997
Revised June 2005
7
4
VC
X16
373 Lo
w
V
o
lt
age
16-
Bit
T
r
ansp
arent
Lat
ch
w
i
th
3.
6V T
o
l
e
rant
I
nput
s
and
O
u
t
put
s
74VCX16373
Low Voltage 16-Bit Transparent Latch
with 3.6V Tolerant Inputs and Outputs
General Description
The VCX16373 contains sixteen non-inverting latches with
3-STATE outputs and is intended for bus oriented applica-
tions. The device is byte controlled. The flip-flops appear to
be transparent to the data when the Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup time
is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
a high impedance state.
The 74VCX16373 is designed for low voltage (1.2V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The 74VCX16373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
a73 1.2V to 3.6V V
CC
supply operation
a73 3.6V tolerant inputs and outputs
a73 t
PD
(I
n
to O
n
)
3.0 ns max for 3.0V to 3.6V V
CC
a73 Power-off high impedance inputs and outputs
a73 Support live insertion and withdrawal (Note 1)
a73 Static Drive (I
OH
/I
OL
)
c11424 mA @ 3.0V V
CC
a73 Uses patented noise/EMI reduction circuitry
a73 Latch-up performance exceeds 300 mA
a73 ESD performance:
Human body model c33 2000V
Machine model c33 200V
a73 Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Note 2: Ordering Code “G” indicates Trays.
Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Order Number Package Number Package Description
74VCX16373G
(Note 2)(Note 3)
BGA54A
(Preliminary)
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74VCX16373MTD
(Note 3)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide