74VCX162839
器件描述：Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs and 26ヘ Series Resistors in the Outputs
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：61.2KB，共7页
Sponsor by e络盟器件资料摘要：
© 1999 Fairchild Semiconductor Corporation DS500127 www.fairchildsemi.com
March 1998
Revised July 1999
7
4
VC
X16
2839
L
o
w
V
o
lt
age 20-Bi
t Selec
t
abl
e
Regi
st
er/
B
uff
e
r w
i
th 3.
6V
T
o
l
e
rant
I
nput
s
and Output
s and
26
Ω
Ser
i
es
Resi
stor
s i
n
the
Output
s
74VCX162839
Low Voltage 20-Bit Selectable Register/Buffer with
3.6V Tolerant Inputs and Outputs
and 26Ω Series Resistors in the Outputs
General Description
The VCX162839 contains twenty non-inverting selectable
buffered or registered paths. The device can be configured
to operate in a registered, or flow through buffer mode by
utilizing the register enable (REGE) and Clock (CP) sig-
nals. The device operates in a 20-bit word wide mode. All
outputs can be placed into 3-STATE through use of the OE
pin. These devices are ideally suited for buffered or regis-
tered 168 pin and 200 pin SDRAM DIMM memory mod-
ules.
The 74VCX162839 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The 74VCX162839 is also designed with 26Ω series resis-
tors in the outputs. This design reduces line noise in appli-
cations such as memory address drivers, clock drivers, and
bus transceivers/transmitters.
The 74VCX162839 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
a73 Compatible with PC100 and PC133 DIMM module
specifications
a73 1.65V–3.6V V
CC
supply operation
a73 3.6V tolerant inputs and outputs
a73 26Ω series resistors in the outputs
a73 t
PD
(CP to O
n
)
4.1 ns max for 3.0V to 3.6V V
CC
5.8 ns max for 2.3V to 2.7V V
CC
9.8 ns max for 1.65V to 1.95V V
CC
a73 Power-off high impedance inputs and outputs
a73 Supports live insertion and withdrawal (Note 1)
a73 Static Drive (I
OH
/I
OL
)
±12 mA @ 3.0V V
CC
±8 mA @ 2.3V V
CC
±3 mA @ 1.65V V
CC
a73 Uses patented noise/EMI reduction circuitry
a73 Latch-up performance exceeds 300 mA
a73 ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol Pin Descriptions
Order Number Package Number Package Description
74VCX162839MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
OE Output Enable Input (Active LOW)
I
0
–I
19
Inputs
O
0
–O
19
Outputs
CP Clock Pulse Input
REGE Register Enable Input
March 1998
Revised July 1999
7
4
VC
X16
2839
L
o
w
V
o
lt
age 20-Bi
t Selec
t
abl
e
Regi
st
er/
B
uff
e
r w
i
th 3.
6V
T
o
l
e
rant
I
nput
s
and Output
s and
26
Ω
Ser
i
es
Resi
stor
s i
n
the
Output
s
74VCX162839
Low Voltage 20-Bit Selectable Register/Buffer with
3.6V Tolerant Inputs and Outputs
and 26Ω Series Resistors in the Outputs
General Description
The VCX162839 contains twenty non-inverting selectable
buffered or registered paths. The device can be configured
to operate in a registered, or flow through buffer mode by
utilizing the register enable (REGE) and Clock (CP) sig-
nals. The device operates in a 20-bit word wide mode. All
outputs can be placed into 3-STATE through use of the OE
pin. These devices are ideally suited for buffered or regis-
tered 168 pin and 200 pin SDRAM DIMM memory mod-
ules.
The 74VCX162839 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The 74VCX162839 is also designed with 26Ω series resis-
tors in the outputs. This design reduces line noise in appli-
cations such as memory address drivers, clock drivers, and
bus transceivers/transmitters.
The 74VCX162839 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
a73 Compatible with PC100 and PC133 DIMM module
specifications
a73 1.65V–3.6V V
CC
supply operation
a73 3.6V tolerant inputs and outputs
a73 26Ω series resistors in the outputs
a73 t
PD
(CP to O
n
)
4.1 ns max for 3.0V to 3.6V V
CC
5.8 ns max for 2.3V to 2.7V V
CC
9.8 ns max for 1.65V to 1.95V V
CC
a73 Power-off high impedance inputs and outputs
a73 Supports live insertion and withdrawal (Note 1)
a73 Static Drive (I
OH
/I
OL
)
±12 mA @ 3.0V V
CC
±8 mA @ 2.3V V
CC
±3 mA @ 1.65V V
CC
a73 Uses patented noise/EMI reduction circuitry
a73 Latch-up performance exceeds 300 mA
a73 ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol Pin Descriptions
Order Number Package Number Package Description
74VCX162839MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
OE Output Enable Input (Active LOW)
I
0
–I
19
Inputs
O
0
–O
19
Outputs
CP Clock Pulse Input
REGE Register Enable Input