74VCX162374MTD
器件描述：Low Voltage 16-Bit D-Type Flip-Flop with 3.6V Tolerant Inputs and Outputs and 26ヘ Series Resistors in Outputs
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：151.55KB，共8页
Sponsor by e络盟器件资料摘要：
© 2000 Fairchild Semiconductor Corporation DS500235 www.fairchildsemi.com
January 2000
Revised January 2000
7
4
VC
X16
2374
L
o
w
V
o
lt
age 16-Bi
t D-T
ype Fli
p
-
F
lop
74VCX162374
Low Voltage 16-Bit D-Type Flip-Flop
with 3.6V Tolerant Inputs and Outputs
and 26Ω Series Resistors in Outputs
General Description
The VCX162374 contains sixteen non-inverting D-type flip-
flops with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. A buffered clock
(CP) and output enable (OE) are common to each byte and
can be shorted together for full 16-bit operation.
The VCX162374 is also designed with 26Ω series resistors
in the outputs. This design reduces line noise in applica-
tions such as memory address drivers, clock drivers and
bus transceivers/transmitters.
The 74VCX162374 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The 74VCX162374 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
a73 1.65V–3.6V V
CC
supply operation
a73 3.6V tolerant inputs and outputs
a73 26Ω series resistors in outputs
a73 t
PD
(CLK to O
n
)
3.4 ns max for 3.0V to 3.6V V
CC
4.8 ns max for 2.3V to 2.7V V
CC
9.6 ns max for 1.65V to 1.95V V
CC
a73 Power-off high impedance inputs and outputs
a73 Supports live insertion and withdrawal (Note 1)
a73 Static Drive (I
OH
/I
OL
)
±12 mA @ 3.0V V
CC
±8 mA @ 2.3V V
CC
±3 mA @ 1.65V V
CC
a73 Uses patented noise/EMI reduction circuitry
a73 Latch-up performance exceeds 300 mA
a73 ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol Pin Descriptions
Order Number
Package
Package Descriptions
Number
74VCX162374MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
OE
n
Output Enable Input (Active LOW)
CP
n
Clock Pulse Input
I
0
–I
15
Inputs
O
0
–O
15
Outputs
January 2000
Revised January 2000
7
4
VC
X16
2374
L
o
w
V
o
lt
age 16-Bi
t D-T
ype Fli
p
-
F
lop
74VCX162374
Low Voltage 16-Bit D-Type Flip-Flop
with 3.6V Tolerant Inputs and Outputs
and 26Ω Series Resistors in Outputs
General Description
The VCX162374 contains sixteen non-inverting D-type flip-
flops with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. A buffered clock
(CP) and output enable (OE) are common to each byte and
can be shorted together for full 16-bit operation.
The VCX162374 is also designed with 26Ω series resistors
in the outputs. This design reduces line noise in applica-
tions such as memory address drivers, clock drivers and
bus transceivers/transmitters.
The 74VCX162374 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The 74VCX162374 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
a73 1.65V–3.6V V
CC
supply operation
a73 3.6V tolerant inputs and outputs
a73 26Ω series resistors in outputs
a73 t
PD
(CLK to O
n
)
3.4 ns max for 3.0V to 3.6V V
CC
4.8 ns max for 2.3V to 2.7V V
CC
9.6 ns max for 1.65V to 1.95V V
CC
a73 Power-off high impedance inputs and outputs
a73 Supports live insertion and withdrawal (Note 1)
a73 Static Drive (I
OH
/I
OL
)
±12 mA @ 3.0V V
CC
±8 mA @ 2.3V V
CC
±3 mA @ 1.65V V
CC
a73 Uses patented noise/EMI reduction circuitry
a73 Latch-up performance exceeds 300 mA
a73 ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol Pin Descriptions
Order Number
Package
Package Descriptions
Number
74VCX162374MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
OE
n
Output Enable Input (Active LOW)
CP
n
Clock Pulse Input
I
0
–I
15
Inputs
O
0
–O
15
Outputs